Maple: a simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays

Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki

Research output: Contribution to journalConference article

12 Citations (Scopus)

Abstract

Technology mapping algorithms for LUT (Look Up Table) based FPGAs have been proposed to transfer a Boolean network into logic-blocks. However, since those algorithms take no layout information into account, they do not always lead to excellent results. In this paper, a simultaneous technology mapping, placement and global routing algorithm for FPGAs, Maple, is presented. Maple is an extended version of a simultaneous placement and global routing algorithm for FPGAs, which is based on recursive partition of layout regions and block sets. Maple inherits its basic process and executes the technology mapping simultaneously in each recursive process. Therefore, the mapping can be done with the placement and global routing information. Experimental results for some benchmark circuits demonstrate its efficiency and effectiveness.

Original languageEnglish
Pages (from-to)156-163
Number of pages8
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication statusPublished - 1994 Dec 1
EventProceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design - San Jose, CA, USA
Duration: 1994 Nov 61994 Nov 10

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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