Maple: A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays

Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki

Research output: Contribution to journalArticle

Abstract

Technology mapping algorithms for LUT (Look Up Table) based FPGAs have been proposed to transfer a Boolean network into logic-blocks. However, since those algorithms take no layout information into account, they do not always lead to excellent results. In this paper, a simultaneous technology mapping, placement and global routing algorithm for FPGAs, Maple, is presented. Maple is an extended version of a simultaneous placement and global routing algorithm for FPGAs, which is based on recursive partition of layout regions and block sets. Maple inherits its basic process and executes the technology mapping simultaneously in each recursive process. Therefore, the mapping can be done with the placement and global routing information. Experimental results for some benchmark circuits demonstrate its efficiency and effectiveness.

Original languageEnglish
Pages (from-to)2028-2038
Number of pages11
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE77-A
Issue number12
Publication statusPublished - 1994 Dec 1

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

Fingerprint Dive into the research topics of 'Maple: A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays'. Together they form a unique fingerprint.

  • Cite this