Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory

Shin ichi Kobayashi, Hiroaki Nakai, Yuichi Kunori, Takeshi Nakayama, Yoshikazu Miyawaki, Yasushi Terada, Hiroshi Onoda, Natsuo Ajika, Masahiro Hatanaka, Hirokazu Miyoshi, Tsutomu Yoshihara

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Abstract

A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low Vcc and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 μm, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.8 × 1.6 μm2 and the chip measures 5.8 × 5.0 mm2. The divided bit line structure realizes a small NOR type memory cell.

Original languageEnglish
Pages (from-to)454-458
Number of pages5
JournalIEEE Journal of Solid-State Circuits
Volume29
Issue number4
DOIs
Publication statusPublished - 1994 Apr
Externally publishedYes

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Kobayashi, S. I., Nakai, H., Kunori, Y., Nakayama, T., Miyawaki, Y., Terada, Y., Onoda, H., Ajika, N., Hatanaka, M., Miyoshi, H., & Yoshihara, T. (1994). Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory. IEEE Journal of Solid-State Circuits, 29(4), 454-458. https://doi.org/10.1109/4.280695