Memory array architecture and decoding scheme for 3V only sector erasable DINOR flash memory

Shi ichi Kobayashi, Hiroaki Nakat, Yuichi Kunori, Takeshi Nakayama, Yoshikazu Miyawaki, Yasushi Terada, Hiroshi Onoda, Natsuo Ajika, Masahiro Hatanaka, Hirokazu Misyoshi, Tsutomu Yoshihara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Several memory array configurations have been proposed for single power supply flash memories. This scheme realizes 1K byte sector erasure with minimized disturbance to the unselected sectors. A memory array configuration and a decoder circuits for the DINOR flash memory have been described. The hierarchical row decoder and the compact source line driver realize 1K byte sector erasure without increasing the decoder area. The decoder pitch has been relaxed to one driver per two word lines. Narrow threshold voltage distribution has been realized by the bit-by-bit programming control and the low threshold voltage detection circuit, which achieves high speed random access time t low Vcc .

Original languageEnglish
Title of host publication1993 Symposium on VLSI Circuits Digest of Technical Papers
Place of PublicationPiscataway, NJ, United States
PublisherPubl by IEEE
Pages97-98
Number of pages2
ISBN (Print)0780312619
Publication statusPublished - 1993
Externally publishedYes
Event1993 Symposium on VLSI Circuits Digest of Technical Papers - Kyoto, Jpn
Duration: 1993 May 191993 May 21

Other

Other1993 Symposium on VLSI Circuits Digest of Technical Papers
CityKyoto, Jpn
Period93/5/1993/5/21

ASJC Scopus subject areas

  • Engineering(all)

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    Kobayashi, S. I., Nakat, H., Kunori, Y., Nakayama, T., Miyawaki, Y., Terada, Y., Onoda, H., Ajika, N., Hatanaka, M., Misyoshi, H., & Yoshihara, T. (1993). Memory array architecture and decoding scheme for 3V only sector erasable DINOR flash memory. In 1993 Symposium on VLSI Circuits Digest of Technical Papers (pp. 97-98). Publ by IEEE.