Memory design using a one-transistor gain cell on SOI

Takashi Ohsawa; Katsuyuki Fujita; Tomoki Higashi; Yoshihisa Iwata; Takeshi Kajiyama; Yoshiyuki Asao; Kazumasa Sunouchi

doi:10.1109/JSSC.2002.802359

Memory design using a one-transistor gain cell on SOI

Takashi Ohsawa^*, Katsuyuki Fujita, Tomoki Higashi, Yoshihisa Iwata, Takeshi Kajiyama, Yoshiyuki Asao, Kazumasa Sunouchi

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

55 Citations (Scopus)

Abstract

A 512-kb memory has been developed featuring a one-transistor gain cell of size 7F²(F = 0.18 μm) on SOI. The cell named the floating body transistor cell (FBC) has the ability to achieve a 4F² cell using self-aligned contact technologies and is proved to be scalable with respect to a cell signal. A basic operation was verified by device simulation and hardware measurement. An array driving method is disclosed which makes selective write possible. A cell signal sensing system consisting of a pair of reference cells written opposite data and comparing the combined current with the doubled cell current is shown to be robust against cell parameter variations in process and temperature. A random access time of 40 ns was simulated. Nondestructive readout and C_b/C_s free signal development drastically improve cell efficiency.

Original language	English
Pages (from-to)	1510-1522
Number of pages	13
Journal	IEEE Journal of Solid-State Circuits
Volume	37
Issue number	11
DOIs	https://doi.org/10.1109/JSSC.2002.802359
Publication status	Published - 2002 Nov
Externally published	Yes

Keywords

Capacitor-less DRAM
DRAM
Embedded memory
Floating body transistor cell
Gain cell
Nondestructive readout
Silicon-on-insulator technology

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/JSSC.2002.802359

Cite this

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title = "Memory design using a one-transistor gain cell on SOI",

abstract = "A 512-kb memory has been developed featuring a one-transistor gain cell of size 7F2(F = 0.18 μm) on SOI. The cell named the floating body transistor cell (FBC) has the ability to achieve a 4F2 cell using self-aligned contact technologies and is proved to be scalable with respect to a cell signal. A basic operation was verified by device simulation and hardware measurement. An array driving method is disclosed which makes selective write possible. A cell signal sensing system consisting of a pair of reference cells written opposite data and comparing the combined current with the doubled cell current is shown to be robust against cell parameter variations in process and temperature. A random access time of 40 ns was simulated. Nondestructive readout and Cb/Cs free signal development drastically improve cell efficiency.",

keywords = "Capacitor-less DRAM, DRAM, Embedded memory, Floating body transistor cell, Gain cell, Nondestructive readout, Silicon-on-insulator technology",

author = "Takashi Ohsawa and Katsuyuki Fujita and Tomoki Higashi and Yoshihisa Iwata and Takeshi Kajiyama and Yoshiyuki Asao and Kazumasa Sunouchi",

year = "2002",

month = nov,

doi = "10.1109/JSSC.2002.802359",

language = "English",

volume = "37",

pages = "1510--1522",

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T1 - Memory design using a one-transistor gain cell on SOI

AU - Ohsawa, Takashi

AU - Fujita, Katsuyuki

AU - Higashi, Tomoki

AU - Iwata, Yoshihisa

AU - Kajiyama, Takeshi

AU - Asao, Yoshiyuki

AU - Sunouchi, Kazumasa

PY - 2002/11

Y1 - 2002/11

N2 - A 512-kb memory has been developed featuring a one-transistor gain cell of size 7F2(F = 0.18 μm) on SOI. The cell named the floating body transistor cell (FBC) has the ability to achieve a 4F2 cell using self-aligned contact technologies and is proved to be scalable with respect to a cell signal. A basic operation was verified by device simulation and hardware measurement. An array driving method is disclosed which makes selective write possible. A cell signal sensing system consisting of a pair of reference cells written opposite data and comparing the combined current with the doubled cell current is shown to be robust against cell parameter variations in process and temperature. A random access time of 40 ns was simulated. Nondestructive readout and Cb/Cs free signal development drastically improve cell efficiency.

AB - A 512-kb memory has been developed featuring a one-transistor gain cell of size 7F2(F = 0.18 μm) on SOI. The cell named the floating body transistor cell (FBC) has the ability to achieve a 4F2 cell using self-aligned contact technologies and is proved to be scalable with respect to a cell signal. A basic operation was verified by device simulation and hardware measurement. An array driving method is disclosed which makes selective write possible. A cell signal sensing system consisting of a pair of reference cells written opposite data and comparing the combined current with the doubled cell current is shown to be robust against cell parameter variations in process and temperature. A random access time of 40 ns was simulated. Nondestructive readout and Cb/Cs free signal development drastically improve cell efficiency.

KW - Capacitor-less DRAM

KW - DRAM

KW - Embedded memory

KW - Floating body transistor cell

KW - Gain cell

KW - Nondestructive readout

KW - Silicon-on-insulator technology

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JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

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ER -

Memory design using a one-transistor gain cell on SOI

Abstract

Keywords

ASJC Scopus subject areas

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