Memory design using one-transistor gain cell on SOI

Takashi Ohsawa, Katsuyuki Fujita, Tomoki Higashi, Yoshihisa Iwata, Takeshi Kajiyama, Yoshiaki Asao, Kazumasa Sunouchi

Research output: Contribution to journalArticle

Abstract

A 512 kb DRAM has a 7F2 one-transistor gain cell (F=0.18 μm) on SOI. The array driving method makes selective write possible. Basic operation is verified by device simulation and hardware measurement. Simulations show 40 ns access time. Non-destructive readout and Cb/Cs-free signal development improve cell efficiency.

Original languageEnglish
Pages (from-to)114-115+425
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Issue numberSUPPL.
Publication statusPublished - 2002
Externally publishedYes

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Dynamic random access storage
Transistors
Hardware
Data storage equipment

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Ohsawa, T., Fujita, K., Higashi, T., Iwata, Y., Kajiyama, T., Asao, Y., & Sunouchi, K. (2002). Memory design using one-transistor gain cell on SOI. Digest of Technical Papers - IEEE International Solid-State Circuits Conference, (SUPPL.), 114-115+425.

Memory design using one-transistor gain cell on SOI. / Ohsawa, Takashi; Fujita, Katsuyuki; Higashi, Tomoki; Iwata, Yoshihisa; Kajiyama, Takeshi; Asao, Yoshiaki; Sunouchi, Kazumasa.

In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference, No. SUPPL., 2002, p. 114-115+425.

Research output: Contribution to journalArticle

Ohsawa, T, Fujita, K, Higashi, T, Iwata, Y, Kajiyama, T, Asao, Y & Sunouchi, K 2002, 'Memory design using one-transistor gain cell on SOI', Digest of Technical Papers - IEEE International Solid-State Circuits Conference, no. SUPPL., pp. 114-115+425.
Ohsawa, Takashi ; Fujita, Katsuyuki ; Higashi, Tomoki ; Iwata, Yoshihisa ; Kajiyama, Takeshi ; Asao, Yoshiaki ; Sunouchi, Kazumasa. / Memory design using one-transistor gain cell on SOI. In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2002 ; No. SUPPL. pp. 114-115+425.
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