Memory-efficient accelerating schedule for LDPC decoder

Kazunori Shimizu; Nozomu Togawa; Takeshi Ikenaga; Satoshi Goto

doi:10.1109/APCCAS.2006.342426

Memory-efficient accelerating schedule for LDPC decoder

Kazunori Shimizu^*, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper proposes a memory-efficient accelerating schedule for LDPC decoder. Important properties of the proposed techniques are as follows: (i) Partitioning a pipelined operation not to read and write intermediate messages simultaneously enables the accelerated message-passing schedule to be implemented with single-port memories. (ii) FIFO-based buffering reduces the number of memory banks and words for the decoder based on the accelerated message-passing schedule. The proposed decoder reduces the memories for intermediate messages by half compared to the conventional one based on the accelerated message-passing schedule.

Original language	English
Title of host publication	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Pages	1317-1320
Number of pages	4
DOIs	https://doi.org/10.1109/APCCAS.2006.342426
Publication status	Published - 2006 Dec 1
Event	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems - , Singapore Duration: 2006 Dec 4 → 2006 Dec 6

Publication series

Name	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

Conference	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Country/Territory	Singapore
Period	06/12/4 → 06/12/6

Keywords

FIFO buffer
FPGA
Low-density parity-check codes
Message-passing algorithm

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/APCCAS.2006.342426

Cite this

Memory-efficient accelerating schedule for LDPC decoder. / Shimizu, Kazunori; Togawa, Nozomu ; Ikenaga, Takeshi et al.

APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems. 2006. p. 1317-1320 4145643 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Shimizu, K, Togawa, N , Ikenaga, T & Goto, S 2006, Memory-efficient accelerating schedule for LDPC decoder. in APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems., 4145643, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, pp. 1317-1320, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, Singapore, 06/12/4. https://doi.org/10.1109/APCCAS.2006.342426

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title = "Memory-efficient accelerating schedule for LDPC decoder",

abstract = "This paper proposes a memory-efficient accelerating schedule for LDPC decoder. Important properties of the proposed techniques are as follows: (i) Partitioning a pipelined operation not to read and write intermediate messages simultaneously enables the accelerated message-passing schedule to be implemented with single-port memories. (ii) FIFO-based buffering reduces the number of memory banks and words for the decoder based on the accelerated message-passing schedule. The proposed decoder reduces the memories for intermediate messages by half compared to the conventional one based on the accelerated message-passing schedule.",

keywords = "FIFO buffer, FPGA, Low-density parity-check codes, Message-passing algorithm",

author = "Kazunori Shimizu and Nozomu Togawa and Takeshi Ikenaga and Satoshi Goto",

year = "2006",

month = dec,

day = "1",

doi = "10.1109/APCCAS.2006.342426",

language = "English",

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series = "IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS",

pages = "1317--1320",

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note = "APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems ; Conference date: 04-12-2006 Through 06-12-2006",

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T1 - Memory-efficient accelerating schedule for LDPC decoder

AU - Shimizu, Kazunori

AU - Togawa, Nozomu

AU - Ikenaga, Takeshi

AU - Goto, Satoshi

PY - 2006/12/1

Y1 - 2006/12/1

N2 - This paper proposes a memory-efficient accelerating schedule for LDPC decoder. Important properties of the proposed techniques are as follows: (i) Partitioning a pipelined operation not to read and write intermediate messages simultaneously enables the accelerated message-passing schedule to be implemented with single-port memories. (ii) FIFO-based buffering reduces the number of memory banks and words for the decoder based on the accelerated message-passing schedule. The proposed decoder reduces the memories for intermediate messages by half compared to the conventional one based on the accelerated message-passing schedule.

AB - This paper proposes a memory-efficient accelerating schedule for LDPC decoder. Important properties of the proposed techniques are as follows: (i) Partitioning a pipelined operation not to read and write intermediate messages simultaneously enables the accelerated message-passing schedule to be implemented with single-port memories. (ii) FIFO-based buffering reduces the number of memory banks and words for the decoder based on the accelerated message-passing schedule. The proposed decoder reduces the memories for intermediate messages by half compared to the conventional one based on the accelerated message-passing schedule.

KW - FIFO buffer

KW - FPGA

KW - Low-density parity-check codes

KW - Message-passing algorithm

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DO - 10.1109/APCCAS.2006.342426

M3 - Conference contribution

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SN - 9781424403875

T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

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BT - APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems

T2 - APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems

Y2 - 4 December 2006 through 6 December 2006

ER -

Memory-efficient accelerating schedule for LDPC decoder

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

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