Memory-efficient accelerating schedule for LDPC decoder

Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper proposes a memory-efficient accelerating schedule for LDPC decoder. Important properties of the proposed techniques are as follows: (i) Partitioning a pipelined operation not to read and write intermediate messages simultaneously enables the accelerated message-passing schedule to be implemented with single-port memories. (ii) FIFO-based buffering reduces the number of memory banks and words for the decoder based on the accelerated message-passing schedule. The proposed decoder reduces the memories for intermediate messages by half compared to the conventional one based on the accelerated message-passing schedule.

Original languageEnglish
Title of host publicationIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
Pages1317-1320
Number of pages4
DOIs
Publication statusPublished - 2006
EventAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems -
Duration: 2006 Dec 42006 Dec 6

Other

OtherAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Period06/12/406/12/6

Fingerprint

Message passing
Data storage equipment

Keywords

  • FIFO buffer
  • FPGA
  • Low-density parity-check codes
  • Message-passing algorithm

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Shimizu, K., Togawa, N., Ikenaga, T., & Goto, S. (2006). Memory-efficient accelerating schedule for LDPC decoder. In IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS (pp. 1317-1320). [4145643] https://doi.org/10.1109/APCCAS.2006.342426

Memory-efficient accelerating schedule for LDPC decoder. / Shimizu, Kazunori; Togawa, Nozomu; Ikenaga, Takeshi; Goto, Satoshi.

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. 2006. p. 1317-1320 4145643.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Shimizu, K, Togawa, N, Ikenaga, T & Goto, S 2006, Memory-efficient accelerating schedule for LDPC decoder. in IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS., 4145643, pp. 1317-1320, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, 06/12/4. https://doi.org/10.1109/APCCAS.2006.342426
Shimizu K, Togawa N, Ikenaga T, Goto S. Memory-efficient accelerating schedule for LDPC decoder. In IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. 2006. p. 1317-1320. 4145643 https://doi.org/10.1109/APCCAS.2006.342426
Shimizu, Kazunori ; Togawa, Nozomu ; Ikenaga, Takeshi ; Goto, Satoshi. / Memory-efficient accelerating schedule for LDPC decoder. IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. 2006. pp. 1317-1320
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