Memory management for data localization on OSCAR chip multiprocessor

Hirofumi Nakano, Takeshi Kodaka, Keiji Kimura, Hironori Kasahara

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)

    Abstract

    Chip Multiprocessor (CMP) architecture has attracting much attention as a next-generation microprocessor architecture and many kinds of CMP are widely being researched. However, CMP architectures several difficulties for effective use of memory, especially cache or local memory near a processor core. The authors have proposed OSCAR CMP architecture, which cooperatively works with multigrain parallelizing compiler which gives us much higher parallelism than instruction level parallelism or loop level parallelism and high productivity of application programs. To support the compiler optimization for effective use of cache or local memory, OSCAR CMP has local data memory (LDM) for processor private data and distributed shared memory (DSM) for synchronization and fine grain data transfers among processors, in addition to centralized shared memory (CSM) to support dynamic task scheduling. This paper proposes a static coarse grain task scheduling scheme for data localization using live variable analysis. Furthermore, remote memory data transfer scheduling scheme using information of live variable analysis is also described. The proposed scheme is implemented on OSCAR FORTRAN multigrain parallelizing compiler and is evaluated on OSCAR CMP using Tomcatv and Swim in SPEC CFP 95 benchmark.

    Original languageEnglish
    Title of host publicationProceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems
    EditorsA. Veidenbaum, H. Nakajo
    Pages82-88
    Number of pages7
    DOIs
    Publication statusPublished - 2004
    EventProceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2004 - Maui, HI
    Duration: 2004 Jan 122004 Jan 14

    Other

    OtherProceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2004
    CityMaui, HI
    Period04/1/1204/1/14

    Fingerprint

    Data storage equipment
    Scheduling
    Data transfer
    Cache memory
    Application programs
    Microprocessor chips
    Synchronization
    Productivity

    ASJC Scopus subject areas

    • Computer Science(all)

    Cite this

    Nakano, H., Kodaka, T., Kimura, K., & Kasahara, H. (2004). Memory management for data localization on OSCAR chip multiprocessor. In A. Veidenbaum, & H. Nakajo (Eds.), Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems (pp. 82-88) https://doi.org/10.1109/IWIA.2004.10020

    Memory management for data localization on OSCAR chip multiprocessor. / Nakano, Hirofumi; Kodaka, Takeshi; Kimura, Keiji; Kasahara, Hironori.

    Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems. ed. / A. Veidenbaum; H. Nakajo. 2004. p. 82-88.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Nakano, H, Kodaka, T, Kimura, K & Kasahara, H 2004, Memory management for data localization on OSCAR chip multiprocessor. in A Veidenbaum & H Nakajo (eds), Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems. pp. 82-88, Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2004, Maui, HI, 04/1/12. https://doi.org/10.1109/IWIA.2004.10020
    Nakano H, Kodaka T, Kimura K, Kasahara H. Memory management for data localization on OSCAR chip multiprocessor. In Veidenbaum A, Nakajo H, editors, Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems. 2004. p. 82-88 https://doi.org/10.1109/IWIA.2004.10020
    Nakano, Hirofumi ; Kodaka, Takeshi ; Kimura, Keiji ; Kasahara, Hironori. / Memory management for data localization on OSCAR chip multiprocessor. Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems. editor / A. Veidenbaum ; H. Nakajo. 2004. pp. 82-88
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