Message-based efficient remote memory access on a highly parallel computer EM-X

Yuetsu Kodama, Hirohumi Sakane, N. Mitsuhisa Sato, Hayato Yamana, Shuichi Sakal, Yoshinori Yamaguchl

Research output: Contribution to journalArticle

Abstract

Communication latency is central to multiprocessor design. This study presents the design principles of the EM-X distributed-memory multiprocessor towards tolerating communication latency. The EM-X overlaps computation with communication for latency tolerance by multithreading. In particular, we present two types of hardware support for remote memory access: (1) priority-based packet scheduling for thread invocation, and (2) direct remote memory access. The prioritybased scheduling policy extends a FIFO ordered thread invocation policy to adopt to different computational needs. The direct remote memory access is designed to overlap remote memory operations with thread execution. The 80-processor prototype of EM-X is developed and is operational since December 1995. We execute several programs on the machine and evaluate how the EM-X effectively overlaps computation with communication toward tolerating communication latency for high performance parallel computing.

Original languageEnglish
Pages (from-to)1065-1071
Number of pages7
JournalIEICE Transactions on Information and Systems
VolumeE79-D
Issue number8
Publication statusPublished - 1996
Externally publishedYes

Fingerprint

Data storage equipment
Communication
Scheduling
Parallel processing systems
Computer hardware

Keywords

  • Distributed shared memory
  • Fine grain communication
  • Mitltithread architecture

ASJC Scopus subject areas

  • Information Systems
  • Computer Graphics and Computer-Aided Design
  • Software

Cite this

Kodama, Y., Sakane, H., Mitsuhisa Sato, N., Yamana, H., Sakal, S., & Yamaguchl, Y. (1996). Message-based efficient remote memory access on a highly parallel computer EM-X. IEICE Transactions on Information and Systems, E79-D(8), 1065-1071.

Message-based efficient remote memory access on a highly parallel computer EM-X. / Kodama, Yuetsu; Sakane, Hirohumi; Mitsuhisa Sato, N.; Yamana, Hayato; Sakal, Shuichi; Yamaguchl, Yoshinori.

In: IEICE Transactions on Information and Systems, Vol. E79-D, No. 8, 1996, p. 1065-1071.

Research output: Contribution to journalArticle

Kodama, Y, Sakane, H, Mitsuhisa Sato, N, Yamana, H, Sakal, S & Yamaguchl, Y 1996, 'Message-based efficient remote memory access on a highly parallel computer EM-X', IEICE Transactions on Information and Systems, vol. E79-D, no. 8, pp. 1065-1071.
Kodama, Yuetsu ; Sakane, Hirohumi ; Mitsuhisa Sato, N. ; Yamana, Hayato ; Sakal, Shuichi ; Yamaguchl, Yoshinori. / Message-based efficient remote memory access on a highly parallel computer EM-X. In: IEICE Transactions on Information and Systems. 1996 ; Vol. E79-D, No. 8. pp. 1065-1071.
@article{27e9d801d5d247a5bf49670af1b44a50,
title = "Message-based efficient remote memory access on a highly parallel computer EM-X",
abstract = "Communication latency is central to multiprocessor design. This study presents the design principles of the EM-X distributed-memory multiprocessor towards tolerating communication latency. The EM-X overlaps computation with communication for latency tolerance by multithreading. In particular, we present two types of hardware support for remote memory access: (1) priority-based packet scheduling for thread invocation, and (2) direct remote memory access. The prioritybased scheduling policy extends a FIFO ordered thread invocation policy to adopt to different computational needs. The direct remote memory access is designed to overlap remote memory operations with thread execution. The 80-processor prototype of EM-X is developed and is operational since December 1995. We execute several programs on the machine and evaluate how the EM-X effectively overlaps computation with communication toward tolerating communication latency for high performance parallel computing.",
keywords = "Distributed shared memory, Fine grain communication, Mitltithread architecture",
author = "Yuetsu Kodama and Hirohumi Sakane and {Mitsuhisa Sato}, N. and Hayato Yamana and Shuichi Sakal and Yoshinori Yamaguchl",
year = "1996",
language = "English",
volume = "E79-D",
pages = "1065--1071",
journal = "IEICE Transactions on Information and Systems",
issn = "0916-8532",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "8",

}

TY - JOUR

T1 - Message-based efficient remote memory access on a highly parallel computer EM-X

AU - Kodama, Yuetsu

AU - Sakane, Hirohumi

AU - Mitsuhisa Sato, N.

AU - Yamana, Hayato

AU - Sakal, Shuichi

AU - Yamaguchl, Yoshinori

PY - 1996

Y1 - 1996

N2 - Communication latency is central to multiprocessor design. This study presents the design principles of the EM-X distributed-memory multiprocessor towards tolerating communication latency. The EM-X overlaps computation with communication for latency tolerance by multithreading. In particular, we present two types of hardware support for remote memory access: (1) priority-based packet scheduling for thread invocation, and (2) direct remote memory access. The prioritybased scheduling policy extends a FIFO ordered thread invocation policy to adopt to different computational needs. The direct remote memory access is designed to overlap remote memory operations with thread execution. The 80-processor prototype of EM-X is developed and is operational since December 1995. We execute several programs on the machine and evaluate how the EM-X effectively overlaps computation with communication toward tolerating communication latency for high performance parallel computing.

AB - Communication latency is central to multiprocessor design. This study presents the design principles of the EM-X distributed-memory multiprocessor towards tolerating communication latency. The EM-X overlaps computation with communication for latency tolerance by multithreading. In particular, we present two types of hardware support for remote memory access: (1) priority-based packet scheduling for thread invocation, and (2) direct remote memory access. The prioritybased scheduling policy extends a FIFO ordered thread invocation policy to adopt to different computational needs. The direct remote memory access is designed to overlap remote memory operations with thread execution. The 80-processor prototype of EM-X is developed and is operational since December 1995. We execute several programs on the machine and evaluate how the EM-X effectively overlaps computation with communication toward tolerating communication latency for high performance parallel computing.

KW - Distributed shared memory

KW - Fine grain communication

KW - Mitltithread architecture

UR - http://www.scopus.com/inward/record.url?scp=0030219318&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0030219318&partnerID=8YFLogxK

M3 - Article

VL - E79-D

SP - 1065

EP - 1071

JO - IEICE Transactions on Information and Systems

JF - IEICE Transactions on Information and Systems

SN - 0916-8532

IS - 8

ER -