Method for acceleration of logic simulations

Masayoshi Sakakura, Yoshiaki Fukazawa

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)

    Abstract

    We present a method for acceleration of logic simulations. The logic simulation is mainly used to detect malfunctions in the logical design phase. As the size of logical circuits grows, acceleration of the logic simulation becomes increasingly required. Several acceleration methods have been presented for this purpose. The outstanding feature of our method is that it accelerates the simulation speed in accordance with the dynamic behaviours of target circuits. A global dynamic behaviour is predicted to realize this feature, through the investigation of the relationship among gates in the early stage of the simulation. Using the relationships, a logic simulation is accelerated by a process called 'grouping'. We have confirmed that the dynamic information of the circuits accelerates logical simulation by the evaluation system.

    Original languageEnglish
    Title of host publicationIEEE Region 10's Annual International Conference, Proceedings
    Place of PublicationPiscataway, NJ, United States
    PublisherIEEE
    Pages828-831
    Number of pages4
    Volume2
    Publication statusPublished - 1995
    EventProceedings of the 1994 IEEE Region 10's 9th Annual International Conference (TENCON'94). Part 1 (of 2) - Singapore, Singapore
    Duration: 1994 Aug 221994 Aug 26

    Other

    OtherProceedings of the 1994 IEEE Region 10's 9th Annual International Conference (TENCON'94). Part 1 (of 2)
    CitySingapore, Singapore
    Period94/8/2294/8/26

    Fingerprint

    Networks (circuits)

    ASJC Scopus subject areas

    • Engineering(all)

    Cite this

    Sakakura, M., & Fukazawa, Y. (1995). Method for acceleration of logic simulations. In IEEE Region 10's Annual International Conference, Proceedings (Vol. 2, pp. 828-831). Piscataway, NJ, United States: IEEE.

    Method for acceleration of logic simulations. / Sakakura, Masayoshi; Fukazawa, Yoshiaki.

    IEEE Region 10's Annual International Conference, Proceedings. Vol. 2 Piscataway, NJ, United States : IEEE, 1995. p. 828-831.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Sakakura, M & Fukazawa, Y 1995, Method for acceleration of logic simulations. in IEEE Region 10's Annual International Conference, Proceedings. vol. 2, IEEE, Piscataway, NJ, United States, pp. 828-831, Proceedings of the 1994 IEEE Region 10's 9th Annual International Conference (TENCON'94). Part 1 (of 2), Singapore, Singapore, 94/8/22.
    Sakakura M, Fukazawa Y. Method for acceleration of logic simulations. In IEEE Region 10's Annual International Conference, Proceedings. Vol. 2. Piscataway, NJ, United States: IEEE. 1995. p. 828-831
    Sakakura, Masayoshi ; Fukazawa, Yoshiaki. / Method for acceleration of logic simulations. IEEE Region 10's Annual International Conference, Proceedings. Vol. 2 Piscataway, NJ, United States : IEEE, 1995. pp. 828-831
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