MeV-BORON IMPLANTED BURIED BARRIER FOR SOFT ERROR REDUCTION IN MEGABIT DRAM.

Y. Matsuda, K. Tsukamoto, M. Inuishi, M. Shimizu, M. Asakura, K. Fujishima, J. Komori, Y. Akasaka

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

The soft error rate (SER) reduction by an MeV-boron implanted buried barrier is presented in applying a 1Mbit NMOS DRAM. Improvement by a factor of more than X100 was obtained in the bit line mode SER and also by a factor of X50 in the cell mode SER compared with the HiC structure. With the aid of the buried barrier, less than 100 FIT of the SER would be achieved in megabit DRAM with the storage capacitance of 24fF at 5V operation.

Original languageEnglish
Title of host publicationConference on Solid State Devices and Materials
PublisherJapan Soc of Applied Physics
Pages23-26
Number of pages4
ISBN (Print)4930813212
Publication statusPublished - 1987 Dec 1

Publication series

NameConference on Solid State Devices and Materials

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Matsuda, Y., Tsukamoto, K., Inuishi, M., Shimizu, M., Asakura, M., Fujishima, K., Komori, J., & Akasaka, Y. (1987). MeV-BORON IMPLANTED BURIED BARRIER FOR SOFT ERROR REDUCTION IN MEGABIT DRAM. In Conference on Solid State Devices and Materials (pp. 23-26). (Conference on Solid State Devices and Materials). Japan Soc of Applied Physics.