MH 4: Multiple-supplyvoltages aware high-level synthesis for highintegrated and highfrequency circuits for HDR architectures

    Research output: Contribution to journalArticle

    14 Citations (Scopus)

    Abstract

    In this paper, we propose multiple-supply-voltages aware high-level synthesis algorithm for HDR architectures which realizes high-speed and high-efficient circuits. We propose three new techniques: virtual area estimation, virtual area adaptation, and floorplanning- directed huddling, and integrate them into our HDR architecture synthesis algorithm. Virtual area estimation/adaptation effectively estimates a huddle area by gradually reducing it during iterations, which improves the convergence of our algorithm. Floorplanningdirected huddling determines huddle composition very effectively by performing floorplanning and functional unit assignment inside huddles simultaneously. Experimental results show that our algorithm achieves about 29% run-time-saving compared with the conventional algorithms, and obtains a solution which cannot be obtained by our original algorithm even if a very tight clock constraint is given.

    Original languageEnglish
    Pages (from-to)1414-1422
    Number of pages9
    JournalIEICE Electronics Express
    Volume9
    Issue number17
    DOIs
    Publication statusPublished - 2012

      Fingerprint

    Keywords

    • Distributed-register architecture
    • Energy-optimization
    • High-level synthesis
    • Interconnection delay
    • Multiple supply voltages

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Condensed Matter Physics
    • Electrical and Electronic Engineering

    Cite this