Min-cut based leakage power aware scheduling in high-level synthesis

Nan Wang, Song Chen, Takeshi Yoshimura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

In this paper, we address the problem of scheduling operations into control steps with dual threshold voltage (dual-Vth) technique under timing and resource constraints. We present a min-cut based algorithm for leakage power optimization. The proposed algorithm first initializes all the operations to high-Vth, then iteratively shorten the critical path delay by reassigning the set of operations covering all the critical paths to low-Vth until the timing constraints are met. A modified force-directed scheduling is implemented to schedule operations and to adjust threshold voltage assignments with consideration of resource constraints. During this procedure, mobility overlap graph (MOG) is constructed based on the mobilities of high-Vth operations. To guarantee the resource constraints are satisfied, operations' threshold voltages are adjusted by computing the min-cut of MOG. Experimental results show that our method performs better both in running time and leakage power reduction compared with MWIS-heuristic [3].

Original languageEnglish
Title of host publicationProceedings - International Symposium on Quality Electronic Design, ISQED
Pages164-169
Number of pages6
DOIs
Publication statusPublished - 2013
Event14th International Symposium on Quality Electronic Design, ISQED 2013 - Santa Clara, CA
Duration: 2013 Mar 42013 Mar 6

Other

Other14th International Symposium on Quality Electronic Design, ISQED 2013
CitySanta Clara, CA
Period13/3/413/3/6

Keywords

  • dual-Vth
  • force-directed scheduling
  • leakage power
  • max-flow min-cut

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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  • Cite this

    Wang, N., Chen, S., & Yoshimura, T. (2013). Min-cut based leakage power aware scheduling in high-level synthesis. In Proceedings - International Symposium on Quality Electronic Design, ISQED (pp. 164-169). [6523605] https://doi.org/10.1109/ISQED.2013.6523605