Minimization of fractional wordlength on fixed-point conversion for high-level synthesis

Nobuhiro Doi, Takashi Horiyama, Masaki Nakanishi, Shinji Kimura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Abstract

In the hardware synthesis from high-level language such as C, bit length of variables is one of the key issues on the area and speed optimization. Usually, designers are required to specify the word length of each variable manually, and verify the correctness by the simulation on huge data. In this paper, we propose an optimization method of fractional wold length of floating-point variables in the floating to fixed-point conversion of variables. The amount of round-off errors are formulated with parameters and propagated via data flow graphs. The non-linear programming is used to solve the fractional wordlength minimization problem. The method does not require the simulation on huge data, and is very fast compared to ones based on the simulation. We have shown the effect on several programs.

Original languageEnglish
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Pages80-85
Number of pages6
Publication statusPublished - 2004
EventProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 - Yokohama
Duration: 2004 Jan 272004 Jan 30

Other

OtherProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004
CityYokohama
Period04/1/2704/1/30

Fingerprint

Data flow graphs
High level languages
Nonlinear programming
Hardware
High level synthesis

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Doi, N., Horiyama, T., Nakanishi, M., & Kimura, S. (2004). Minimization of fractional wordlength on fixed-point conversion for high-level synthesis. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 80-85)

Minimization of fractional wordlength on fixed-point conversion for high-level synthesis. / Doi, Nobuhiro; Horiyama, Takashi; Nakanishi, Masaki; Kimura, Shinji.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2004. p. 80-85.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Doi, N, Horiyama, T, Nakanishi, M & Kimura, S 2004, Minimization of fractional wordlength on fixed-point conversion for high-level synthesis. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. pp. 80-85, Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004, Yokohama, 04/1/27.
Doi N, Horiyama T, Nakanishi M, Kimura S. Minimization of fractional wordlength on fixed-point conversion for high-level synthesis. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2004. p. 80-85
Doi, Nobuhiro ; Horiyama, Takashi ; Nakanishi, Masaki ; Kimura, Shinji. / Minimization of fractional wordlength on fixed-point conversion for high-level synthesis. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2004. pp. 80-85
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