Minimizing energy of integer unit by higher voltage flip-flop: V _DDmin-aware dual supply voltage technique

To achieve the most energy-efficient operation, this brief presents a circuit design technique for separating the power supply voltage (V _DD) of flip-flops (FFs) from that of combinational circuits, called the higher voltage FF (HVFF). Although V_DD scaling can reduce the energy, the minimum operating voltage (V_DDmin) of FFs prevents the operation at the optimum supply voltage that minimizes the energy, because the V_DDmin of FFs is higher than the optimum supply voltage. In HVFF, the V_DD of combinational logic gates is reduced below the V _DDmin of FFs while keeping the V_DD of FFs at their V _DDmin. This makes it possible to minimize the energy without power and delay penalties at the nominal supply voltage (1.2 V) as well as without FF topological difications. A 16-bit integer unit with HVFF is fabricated in a 65-nm CMOS process, and measurement results show that HVFF reduces the minimum energy by 13% compared with the conventional operation, which is 1/10 times smaller than the energy at the nominal supply voltage.