Minimizing energy of integer unit by higher voltage flip-flop

V DDmin-aware dual supply voltage technique

Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

To achieve the most energy-efficient operation, this brief presents a circuit design technique for separating the power supply voltage (V DD) of flip-flops (FFs) from that of combinational circuits, called the higher voltage FF (HVFF). Although VDD scaling can reduce the energy, the minimum operating voltage (VDDmin) of FFs prevents the operation at the optimum supply voltage that minimizes the energy, because the VDDmin of FFs is higher than the optimum supply voltage. In HVFF, the VDD of combinational logic gates is reduced below the V DDmin of FFs while keeping the VDD of FFs at their V DDmin. This makes it possible to minimize the energy without power and delay penalties at the nominal supply voltage (1.2 V) as well as without FF topological difications. A 16-bit integer unit with HVFF is fabricated in a 65-nm CMOS process, and measurement results show that HVFF reduces the minimum energy by 13% compared with the conventional operation, which is 1/10 times smaller than the energy at the nominal supply voltage.

Original languageEnglish
Article number6236208
Pages (from-to)1175-1179
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume21
Issue number6
DOIs
Publication statusPublished - 2013
Externally publishedYes

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Flip flop circuits
Electric potential
Combinatorial circuits
Logic gates
Networks (circuits)

Keywords

  • Minimum operating voltage
  • subthreshold circuits
  • variations

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Software

Cite this

Minimizing energy of integer unit by higher voltage flip-flop : V DDmin-aware dual supply voltage technique. / Fuketa, Hiroshi; Hirairi, Koji; Yasufuku, Tadashi; Takamiya, Makoto; Nomura, Masahiro; Shinohara, Hirofumi; Sakurai, Takayasu.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 6, 6236208, 2013, p. 1175-1179.

Research output: Contribution to journalArticle

Fuketa, Hiroshi ; Hirairi, Koji ; Yasufuku, Tadashi ; Takamiya, Makoto ; Nomura, Masahiro ; Shinohara, Hirofumi ; Sakurai, Takayasu. / Minimizing energy of integer unit by higher voltage flip-flop : V DDmin-aware dual supply voltage technique. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2013 ; Vol. 21, No. 6. pp. 1175-1179.
@article{00c0df27ad6d4cffa8af1d8bb5e29279,
title = "Minimizing energy of integer unit by higher voltage flip-flop: V DDmin-aware dual supply voltage technique",
abstract = "To achieve the most energy-efficient operation, this brief presents a circuit design technique for separating the power supply voltage (V DD) of flip-flops (FFs) from that of combinational circuits, called the higher voltage FF (HVFF). Although VDD scaling can reduce the energy, the minimum operating voltage (VDDmin) of FFs prevents the operation at the optimum supply voltage that minimizes the energy, because the VDDmin of FFs is higher than the optimum supply voltage. In HVFF, the VDD of combinational logic gates is reduced below the V DDmin of FFs while keeping the VDD of FFs at their V DDmin. This makes it possible to minimize the energy without power and delay penalties at the nominal supply voltage (1.2 V) as well as without FF topological difications. A 16-bit integer unit with HVFF is fabricated in a 65-nm CMOS process, and measurement results show that HVFF reduces the minimum energy by 13{\%} compared with the conventional operation, which is 1/10 times smaller than the energy at the nominal supply voltage.",
keywords = "Minimum operating voltage, subthreshold circuits, variations",
author = "Hiroshi Fuketa and Koji Hirairi and Tadashi Yasufuku and Makoto Takamiya and Masahiro Nomura and Hirofumi Shinohara and Takayasu Sakurai",
year = "2013",
doi = "10.1109/TVLSI.2012.2203834",
language = "English",
volume = "21",
pages = "1175--1179",
journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
issn = "1063-8210",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "6",

}

TY - JOUR

T1 - Minimizing energy of integer unit by higher voltage flip-flop

T2 - V DDmin-aware dual supply voltage technique

AU - Fuketa, Hiroshi

AU - Hirairi, Koji

AU - Yasufuku, Tadashi

AU - Takamiya, Makoto

AU - Nomura, Masahiro

AU - Shinohara, Hirofumi

AU - Sakurai, Takayasu

PY - 2013

Y1 - 2013

N2 - To achieve the most energy-efficient operation, this brief presents a circuit design technique for separating the power supply voltage (V DD) of flip-flops (FFs) from that of combinational circuits, called the higher voltage FF (HVFF). Although VDD scaling can reduce the energy, the minimum operating voltage (VDDmin) of FFs prevents the operation at the optimum supply voltage that minimizes the energy, because the VDDmin of FFs is higher than the optimum supply voltage. In HVFF, the VDD of combinational logic gates is reduced below the V DDmin of FFs while keeping the VDD of FFs at their V DDmin. This makes it possible to minimize the energy without power and delay penalties at the nominal supply voltage (1.2 V) as well as without FF topological difications. A 16-bit integer unit with HVFF is fabricated in a 65-nm CMOS process, and measurement results show that HVFF reduces the minimum energy by 13% compared with the conventional operation, which is 1/10 times smaller than the energy at the nominal supply voltage.

AB - To achieve the most energy-efficient operation, this brief presents a circuit design technique for separating the power supply voltage (V DD) of flip-flops (FFs) from that of combinational circuits, called the higher voltage FF (HVFF). Although VDD scaling can reduce the energy, the minimum operating voltage (VDDmin) of FFs prevents the operation at the optimum supply voltage that minimizes the energy, because the VDDmin of FFs is higher than the optimum supply voltage. In HVFF, the VDD of combinational logic gates is reduced below the V DDmin of FFs while keeping the VDD of FFs at their V DDmin. This makes it possible to minimize the energy without power and delay penalties at the nominal supply voltage (1.2 V) as well as without FF topological difications. A 16-bit integer unit with HVFF is fabricated in a 65-nm CMOS process, and measurement results show that HVFF reduces the minimum energy by 13% compared with the conventional operation, which is 1/10 times smaller than the energy at the nominal supply voltage.

KW - Minimum operating voltage

KW - subthreshold circuits

KW - variations

UR - http://www.scopus.com/inward/record.url?scp=84878295000&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84878295000&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2012.2203834

DO - 10.1109/TVLSI.2012.2203834

M3 - Article

VL - 21

SP - 1175

EP - 1179

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 6

M1 - 6236208

ER -