Mixed bus width architecture for low cost AES VLSI design

Yibo Fan, Jidong Wang, Takeshi Ikenaga, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

With the increase of security problem, AES is widely used in a lot of secure systems. For some low data throughput applications, low cost design is more attractive than high speed design. In this paper, low cost hardware architecture for AES algorithm is proposed. Mixed bus width architecture is used to reduce hardware cost and shorten critical path. The experimental results show that the lowest hardware cost implementation of AES algorithm is 4678 Gates. The corresponding frequency is 80MHz and the throughput is 51Mbps. This architecture is very suitable for mid-throughput, low power and low hardware cost systems such as mobile system.

Original languageEnglish
Title of host publicationASICON 2007 - 2007 7th International Conference on ASIC Proceeding
Pages854-857
Number of pages4
DOIs
Publication statusPublished - 2007 Dec 1
Event2007 7th International Conference on ASIC, ASICON 2007 - Guilin, China
Duration: 2007 Oct 262007 Oct 29

Publication series

NameASICON 2007 - 2007 7th International Conference on ASIC Proceeding

Conference

Conference2007 7th International Conference on ASIC, ASICON 2007
CountryChina
CityGuilin
Period07/10/2607/10/29

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Mixed bus width architecture for low cost AES VLSI design'. Together they form a unique fingerprint.

  • Cite this

    Fan, Y., Wang, J., Ikenaga, T., & Goto, S. (2007). Mixed bus width architecture for low cost AES VLSI design. In ASICON 2007 - 2007 7th International Conference on ASIC Proceeding (pp. 854-857). [4415765] (ASICON 2007 - 2007 7th International Conference on ASIC Proceeding). https://doi.org/10.1109/ICASIC.2007.4415765