Mixed bus width architecture for low cost AES VLSI design

Yibo Fan, Jidong Wang, Takeshi Ikenaga, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

With the increase of security problem, AES is widely used in a lot of secure systems. For some low data throughput applications, low cost design is more attractive than high speed design. In this paper, low cost hardware architecture for AES algorithm is proposed. Mixed bus width architecture is used to reduce hardware cost and shorten critical path. The experimental results show that the lowest hardware cost implementation of AES algorithm is 4678 Gates. The corresponding frequency is 80MHz and the throughput is 51Mbps. This architecture is very suitable for mid-throughput, low power and low hardware cost systems such as mobile system.

Original languageEnglish
Title of host publicationASICON 2007 - 2007 7th International Conference on ASIC Proceeding
Pages854-857
Number of pages4
DOIs
Publication statusPublished - 2007
Event2007 7th International Conference on ASIC, ASICON 2007 - Guilin
Duration: 2007 Oct 262007 Oct 29

Other

Other2007 7th International Conference on ASIC, ASICON 2007
CityGuilin
Period07/10/2607/10/29

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Hardware
Throughput
Costs

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Fan, Y., Wang, J., Ikenaga, T., & Goto, S. (2007). Mixed bus width architecture for low cost AES VLSI design. In ASICON 2007 - 2007 7th International Conference on ASIC Proceeding (pp. 854-857). [4415765] https://doi.org/10.1109/ICASIC.2007.4415765

Mixed bus width architecture for low cost AES VLSI design. / Fan, Yibo; Wang, Jidong; Ikenaga, Takeshi; Goto, Satoshi.

ASICON 2007 - 2007 7th International Conference on ASIC Proceeding. 2007. p. 854-857 4415765.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fan, Y, Wang, J, Ikenaga, T & Goto, S 2007, Mixed bus width architecture for low cost AES VLSI design. in ASICON 2007 - 2007 7th International Conference on ASIC Proceeding., 4415765, pp. 854-857, 2007 7th International Conference on ASIC, ASICON 2007, Guilin, 07/10/26. https://doi.org/10.1109/ICASIC.2007.4415765
Fan Y, Wang J, Ikenaga T, Goto S. Mixed bus width architecture for low cost AES VLSI design. In ASICON 2007 - 2007 7th International Conference on ASIC Proceeding. 2007. p. 854-857. 4415765 https://doi.org/10.1109/ICASIC.2007.4415765
Fan, Yibo ; Wang, Jidong ; Ikenaga, Takeshi ; Goto, Satoshi. / Mixed bus width architecture for low cost AES VLSI design. ASICON 2007 - 2007 7th International Conference on ASIC Proceeding. 2007. pp. 854-857
@inproceedings{75784964f34e40f7a03139b79bd6b1ce,
title = "Mixed bus width architecture for low cost AES VLSI design",
abstract = "With the increase of security problem, AES is widely used in a lot of secure systems. For some low data throughput applications, low cost design is more attractive than high speed design. In this paper, low cost hardware architecture for AES algorithm is proposed. Mixed bus width architecture is used to reduce hardware cost and shorten critical path. The experimental results show that the lowest hardware cost implementation of AES algorithm is 4678 Gates. The corresponding frequency is 80MHz and the throughput is 51Mbps. This architecture is very suitable for mid-throughput, low power and low hardware cost systems such as mobile system.",
author = "Yibo Fan and Jidong Wang and Takeshi Ikenaga and Satoshi Goto",
year = "2007",
doi = "10.1109/ICASIC.2007.4415765",
language = "English",
isbn = "1424411327",
pages = "854--857",
booktitle = "ASICON 2007 - 2007 7th International Conference on ASIC Proceeding",

}

TY - GEN

T1 - Mixed bus width architecture for low cost AES VLSI design

AU - Fan, Yibo

AU - Wang, Jidong

AU - Ikenaga, Takeshi

AU - Goto, Satoshi

PY - 2007

Y1 - 2007

N2 - With the increase of security problem, AES is widely used in a lot of secure systems. For some low data throughput applications, low cost design is more attractive than high speed design. In this paper, low cost hardware architecture for AES algorithm is proposed. Mixed bus width architecture is used to reduce hardware cost and shorten critical path. The experimental results show that the lowest hardware cost implementation of AES algorithm is 4678 Gates. The corresponding frequency is 80MHz and the throughput is 51Mbps. This architecture is very suitable for mid-throughput, low power and low hardware cost systems such as mobile system.

AB - With the increase of security problem, AES is widely used in a lot of secure systems. For some low data throughput applications, low cost design is more attractive than high speed design. In this paper, low cost hardware architecture for AES algorithm is proposed. Mixed bus width architecture is used to reduce hardware cost and shorten critical path. The experimental results show that the lowest hardware cost implementation of AES algorithm is 4678 Gates. The corresponding frequency is 80MHz and the throughput is 51Mbps. This architecture is very suitable for mid-throughput, low power and low hardware cost systems such as mobile system.

UR - http://www.scopus.com/inward/record.url?scp=48349098241&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=48349098241&partnerID=8YFLogxK

U2 - 10.1109/ICASIC.2007.4415765

DO - 10.1109/ICASIC.2007.4415765

M3 - Conference contribution

AN - SCOPUS:48349098241

SN - 1424411327

SN - 9781424411320

SP - 854

EP - 857

BT - ASICON 2007 - 2007 7th International Conference on ASIC Proceeding

ER -