Mobility overlap-removal-based leakage power and register-aware scheduling in high-level synthesis

Nan Wang, Song Chen, Wei Zhong, Nan Liu, Takeshi Yoshimura

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Scheduling is a key problem in high level synthesis, as the scheduling results affect most of the important design metrics. In this paper, we propose a novel scheduling method to simultaneously optimize the leakage power of functional units with dual-Vth techniques and the number of registers under given timing and resource constraints. The mobility overlaps between operations are removed to eliminate data dependencies, and a simulated-annealing-based method is introduced to explore the mobility overlap removal solution space. Given the overlapfree mobilities, the resource usage and register usage in each control step can be accurately estimated. Meanwhile, operations are scheduled so as to optimize the leakage power of functional units with minimal number of registers. Then, a set of operations is iteratively selected, reassigned as low-Vth, and rescheduled until the resource constraints are all satisfied. Experimental results show the efficiency of the proposed algorithm.

Original languageEnglish
Pages (from-to)1709-1719
Number of pages11
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE97-A
Issue number8
DOIs
Publication statusPublished - 2014

Fingerprint

High-level Synthesis
Leakage
Overlap
Resource Constraints
Scheduling
Optimise
Data Dependency
Unit
Simulated annealing
Simulated Annealing
Timing
Eliminate
Metric
Resources
Experimental Results
High level synthesis

Keywords

  • Dual-Vth
  • High-level synthesis
  • Leakage power
  • Mobility overlap removal
  • Register usage

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Graphics and Computer-Aided Design
  • Applied Mathematics
  • Signal Processing

Cite this

Mobility overlap-removal-based leakage power and register-aware scheduling in high-level synthesis. / Wang, Nan; Chen, Song; Zhong, Wei; Liu, Nan; Yoshimura, Takeshi.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E97-A, No. 8, 2014, p. 1709-1719.

Research output: Contribution to journalArticle

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