Modeling, simulation, fabrication, and characterization of a 10-μ W/cm2 class si-nanowire thermoelectric generator for IoT applications

Motohiro Tomita; Shunsuke Oba; Yuya Himeda; Ryo Yamato; Keisuke Shima; Takehiro Kumada; Mao Xu; Hiroki Takezawa; Kohhei Mesaki; Kazuaki Tsuda; Shuichiro Hashimoto; Tianzhuo Zhan; Hui Zhang; Yoshinari Kamakura; Yuhhei Suzuki; Hiroshi Inokawa; Hiroya Ikeda; Takashi Matsukawa; Takeo Matsuki; Takanobu Watanabe

doi:10.1109/TED.2018.2867845

Modeling, simulation, fabrication, and characterization of a 10-μ W/cm² class si-nanowire thermoelectric generator for IoT applications

Motohiro Tomita^*, Shunsuke Oba, Yuya Himeda, Ryo Yamato, Keisuke Shima, Takehiro Kumada, Mao Xu, Hiroki Takezawa, Kohhei Mesaki, Kazuaki Tsuda, Shuichiro Hashimoto, Tianzhuo Zhan, Hui Zhang, Yoshinari Kamakura, Yuhhei Suzuki, Hiroshi Inokawa, Hiroya Ikeda, Takashi Matsukawa, Takeo Matsuki, Takanobu Watanabe

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

39 Citations (Scopus)

Abstract

We propose a planar device architecture compatible with the CMOS process technology as the optimal current benchmark of a Si-nanowire (NW) thermoelectric (TE) power generator. The proposed device is driven by a temperature gradient that is formed in the proximity of a perpendicular heat flow to the substrate. Therefore, unlike the conventional TE generators, the planar short Si-NWs need not be suspended on a cavity structure. Under an externally applied temperature difference of 5 K, the recorded TE power density is observed to be 12 μW/cm² by shortening the Si-NWs length and suppressing the parasitic thermal resistance of the Si substrate. The demonstration paves a pathway to develop cost-effective autonomous internet-of-things applications that utilize the environmental and body heats.

Original language	English
Article number	8467534
Pages (from-to)	5180-5188
Number of pages	9
Journal	IEEE Transactions on Electron Devices
Volume	65
Issue number	11
DOIs	https://doi.org/10.1109/TED.2018.2867845
Publication status	Published - 2018 Nov
Externally published	Yes

Keywords

CMOS process
Si nanowire (NW)
energy harvesting
scalability
thermoelectric (TE) generator

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/TED.2018.2867845

Cite this

Tomita, M., Oba, S., Himeda, Y., Yamato, R., Shima, K., Kumada, T., Xu, M., Takezawa, H., Mesaki, K., Tsuda, K., Hashimoto, S., Zhan, T., Zhang, H., Kamakura, Y., Suzuki, Y., Inokawa, H., Ikeda, H., Matsukawa, T., Matsuki, T., & Watanabe, T. (2018). Modeling, simulation, fabrication, and characterization of a 10-μ W/cm² class si-nanowire thermoelectric generator for IoT applications. IEEE Transactions on Electron Devices, 65(11), 5180-5188. [8467534]. https://doi.org/10.1109/TED.2018.2867845

Tomita, M, Oba, S, Himeda, Y, Yamato, R, Shima, K, Kumada, T, Xu, M, Takezawa, H, Mesaki, K, Tsuda, K, Hashimoto, S, Zhan, T, Zhang, H, Kamakura, Y, Suzuki, Y, Inokawa, H, Ikeda, H, Matsukawa, T, Matsuki, T & Watanabe, T 2018, 'Modeling, simulation, fabrication, and characterization of a 10-μ W/cm² class si-nanowire thermoelectric generator for IoT applications', IEEE Transactions on Electron Devices, vol. 65, no. 11, 8467534, pp. 5180-5188. https://doi.org/10.1109/TED.2018.2867845

@article{b6dd2a1c8bfb4eba96417408502f3175,

title = "Modeling, simulation, fabrication, and characterization of a 10-μ W/cm2 class si-nanowire thermoelectric generator for IoT applications",

abstract = "We propose a planar device architecture compatible with the CMOS process technology as the optimal current benchmark of a Si-nanowire (NW) thermoelectric (TE) power generator. The proposed device is driven by a temperature gradient that is formed in the proximity of a perpendicular heat flow to the substrate. Therefore, unlike the conventional TE generators, the planar short Si-NWs need not be suspended on a cavity structure. Under an externally applied temperature difference of 5 K, the recorded TE power density is observed to be 12 μW/cm2 by shortening the Si-NWs length and suppressing the parasitic thermal resistance of the Si substrate. The demonstration paves a pathway to develop cost-effective autonomous internet-of-things applications that utilize the environmental and body heats.",

keywords = "CMOS process, Si nanowire (NW), energy harvesting, scalability, thermoelectric (TE) generator",

author = "Motohiro Tomita and Shunsuke Oba and Yuya Himeda and Ryo Yamato and Keisuke Shima and Takehiro Kumada and Mao Xu and Hiroki Takezawa and Kohhei Mesaki and Kazuaki Tsuda and Shuichiro Hashimoto and Tianzhuo Zhan and Hui Zhang and Yoshinari Kamakura and Yuhhei Suzuki and Hiroshi Inokawa and Hiroya Ikeda and Takashi Matsukawa and Takeo Matsuki and Takanobu Watanabe",

note = "Funding Information: Manuscript received June 30, 2018; revised August 17, 2018; accepted August 21, 2018. Date of publication September 18, 2018; date of current version October 22, 2018. This paper was originally presented in 2018 Symposium on VLSI Technology (Honolulu, Hawaii). This work was supported in part by JST-CREST under Grant JPMJCR15Q7, in part by NIMS Nanofabrication Platform, and in part by AIST-SCR. The review of this paper was arranged by Editor G. Ghione. (Corresponding author: Motohiro Tomita.) M. Tomita, S. Oba, Y. Himeda, R. Yamato, K. Shima, T. Kumada, M. Xu, H. Takezawa, K. Mesaki, K. Tsuda, S. Hashimoto, T. Zhan, and T. Watanabe are with the Faculty of Science and Engineering, Waseda University, Tokyo 169-8050, Japan (e-mail: tomita_motohiro@ watanabe.nano.waseda.ac.jp; watanabe-t@waseda.jp). Publisher Copyright: {\textcopyright} 2018 IEEE.",

year = "2018",

month = nov,

doi = "10.1109/TED.2018.2867845",

language = "English",

volume = "65",

pages = "5180--5188",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "11",

}

TY - JOUR

T1 - Modeling, simulation, fabrication, and characterization of a 10-μ W/cm2 class si-nanowire thermoelectric generator for IoT applications

AU - Tomita, Motohiro

AU - Oba, Shunsuke

AU - Himeda, Yuya

AU - Yamato, Ryo

AU - Shima, Keisuke

AU - Kumada, Takehiro

AU - Xu, Mao

AU - Takezawa, Hiroki

AU - Mesaki, Kohhei

AU - Tsuda, Kazuaki

AU - Hashimoto, Shuichiro

AU - Zhan, Tianzhuo

AU - Zhang, Hui

AU - Kamakura, Yoshinari

AU - Suzuki, Yuhhei

AU - Inokawa, Hiroshi

AU - Ikeda, Hiroya

AU - Matsukawa, Takashi

AU - Matsuki, Takeo

AU - Watanabe, Takanobu

N1 - Funding Information: Manuscript received June 30, 2018; revised August 17, 2018; accepted August 21, 2018. Date of publication September 18, 2018; date of current version October 22, 2018. This paper was originally presented in 2018 Symposium on VLSI Technology (Honolulu, Hawaii). This work was supported in part by JST-CREST under Grant JPMJCR15Q7, in part by NIMS Nanofabrication Platform, and in part by AIST-SCR. The review of this paper was arranged by Editor G. Ghione. (Corresponding author: Motohiro Tomita.) M. Tomita, S. Oba, Y. Himeda, R. Yamato, K. Shima, T. Kumada, M. Xu, H. Takezawa, K. Mesaki, K. Tsuda, S. Hashimoto, T. Zhan, and T. Watanabe are with the Faculty of Science and Engineering, Waseda University, Tokyo 169-8050, Japan (e-mail: tomita_motohiro@ watanabe.nano.waseda.ac.jp; watanabe-t@waseda.jp). Publisher Copyright: © 2018 IEEE.

PY - 2018/11

Y1 - 2018/11

N2 - We propose a planar device architecture compatible with the CMOS process technology as the optimal current benchmark of a Si-nanowire (NW) thermoelectric (TE) power generator. The proposed device is driven by a temperature gradient that is formed in the proximity of a perpendicular heat flow to the substrate. Therefore, unlike the conventional TE generators, the planar short Si-NWs need not be suspended on a cavity structure. Under an externally applied temperature difference of 5 K, the recorded TE power density is observed to be 12 μW/cm2 by shortening the Si-NWs length and suppressing the parasitic thermal resistance of the Si substrate. The demonstration paves a pathway to develop cost-effective autonomous internet-of-things applications that utilize the environmental and body heats.

AB - We propose a planar device architecture compatible with the CMOS process technology as the optimal current benchmark of a Si-nanowire (NW) thermoelectric (TE) power generator. The proposed device is driven by a temperature gradient that is formed in the proximity of a perpendicular heat flow to the substrate. Therefore, unlike the conventional TE generators, the planar short Si-NWs need not be suspended on a cavity structure. Under an externally applied temperature difference of 5 K, the recorded TE power density is observed to be 12 μW/cm2 by shortening the Si-NWs length and suppressing the parasitic thermal resistance of the Si substrate. The demonstration paves a pathway to develop cost-effective autonomous internet-of-things applications that utilize the environmental and body heats.

KW - CMOS process

KW - Si nanowire (NW)

KW - energy harvesting

KW - scalability

KW - thermoelectric (TE) generator

UR - http://www.scopus.com/inward/record.url?scp=85053627698&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85053627698&partnerID=8YFLogxK

U2 - 10.1109/TED.2018.2867845

DO - 10.1109/TED.2018.2867845

M3 - Article

AN - SCOPUS:85053627698

VL - 65

SP - 5180

EP - 5188

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

IS - 11

M1 - 8467534

ER -