Abstract
We propose a planar device architecture compatible with the CMOS process technology as the optimal current benchmark of a Si-nanowire (NW) thermoelectric (TE) power generator. The proposed device is driven by a temperature gradient that is formed in the proximity of a perpendicular heat flow to the substrate. Therefore, unlike the conventional TE generators, the planar short Si-NWs need not be suspended on a cavity structure. Under an externally applied temperature difference of 5 K, the recorded TE power density is observed to be 12 μW/cm2 by shortening the Si-NWs length and suppressing the parasitic thermal resistance of the Si substrate. The demonstration paves a pathway to develop cost-effective autonomous internet-of-things applications that utilize the environmental and body heats.
Original language | English |
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Article number | 8467534 |
Pages (from-to) | 5180-5188 |
Number of pages | 9 |
Journal | IEEE Transactions on Electron Devices |
Volume | 65 |
Issue number | 11 |
DOIs | |
Publication status | Published - 2018 Nov |
Keywords
- CMOS process
- Si nanowire (NW)
- energy harvesting
- scalability
- thermoelectric (TE) generator
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering