Modeling the effective capacitance of interconnect loads for predicting CMOS gate slew

Zhangcai Huang, Atsushi Kurokawa, Jun Pan, Yasuaki Inoue

    Research output: Contribution to journalArticle

    6 Citations (Scopus)

    Abstract

    In deep submicron designs, predicting gate slews and delays for interconnect loads is vitally important for Static Timing Analysis (STA). The effective capacitance Ceff concept is usually used to calculate the gate delay of interconnect loads. Many Ceff algorithms have been proposed to compute gate delay of interconnect loads. However, less work has been done to develop a Ceff algorithm which can accurately predict gate slew. In this paper, we propose a novel method for calculating the C eff of interconnect load for gate slew. We firstly establish a new expression for Ceff in 0.8Vdd point. Then the Integration Approximation method is used to calculate the value of Ceff in 0.88Vdd point. In this method, the integration of a complicated nonlinear gate output is approximated with that of a piecewise linear waveform. Based on the value of Ceff in 0.8Vdd point, Ceff of interconnect load for gate slew is obtained. The simulation results demonstrate a significant improvement in accuracy.

    Original languageEnglish
    Pages (from-to)3367-3374
    Number of pages8
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE88-A
    Issue number12
    DOIs
    Publication statusPublished - 2005 Dec

    Keywords

    • CMOS inverter
    • Effective capacitance
    • Gate slew
    • Interconnect loads
    • Static timing analysis

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Hardware and Architecture
    • Information Systems

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