Modeling the impact of input-to-output coupling capacitance on power dissipation estimation in deep submicron CMOS circuits

Huang Zhangcai, Li Na, Huang Sui, Yasuaki Inoue

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    In this paper modeling the impact of input-to-output coupling capacitance on power dissipation estimation in submicron CMOS circuits is proposed. Compared with conventional methods, the proposed model is much accurate because it considers the impact of the input-to-output capacitance on power dissipation estimation. In addition, the proposed model can estimate the impact of coupling capacitance on serial gates. The experimental results show that the proposed model can obtain an considerable improvement in accuracy.

    Original languageEnglish
    Title of host publicationICCCAS 2007 - International Conference on Communications, Circuits and Systems 2007
    Pages1154-1157
    Number of pages4
    Publication statusPublished - 2008
    EventICCCAS 2007 - International Conference on Communications, Circuits and Systems 2007 - Kokura
    Duration: 2007 Jul 112007 Jul 13

    Other

    OtherICCCAS 2007 - International Conference on Communications, Circuits and Systems 2007
    CityKokura
    Period07/7/1107/7/13

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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  • Cite this

    Zhangcai, H., Na, L., Sui, H., & Inoue, Y. (2008). Modeling the impact of input-to-output coupling capacitance on power dissipation estimation in deep submicron CMOS circuits. In ICCCAS 2007 - International Conference on Communications, Circuits and Systems 2007 (pp. 1154-1157). [4348251]