Modeling the influence of input-to-output coupling capacitance on CMOS inverter delay

Zhangcai Huang, Atsushi Kurokawa, Yun Yang, Hong Yu, Yasuaki Inoue

    Research output: Contribution to journalArticle

    1 Citation (Scopus)

    Abstract

    The modeling of gate delays has always been one of the most difficult and market-sensitive works. In submicron designs, the second-order effects such as the input-to-output coupling capacitance have a significant influence on gate delay as shown in this paper. However, the accurate analysis of the input-to-output coupling capacitance effect has not been presented in previous research. In this paper, an analytical model for the influence of the input-to-output coupling capacitance on CMOS inverter delay is proposed, in which a novel algorithm for computing overshooting time is given. Experimental results show good agreement with Spice simulations.

    Original languageEnglish
    Pages (from-to)840-846
    Number of pages7
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE89-A
    Issue number4
    DOIs
    Publication statusPublished - 2006 Apr

    Keywords

    • CMOS inverter
    • Deep submicron
    • Overshooting effect
    • Timing analysis

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Hardware and Architecture
    • Information Systems

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