Modeling the overshooting effect for CMOS inverter delay analysis in nanometer technologies

Zhangcai Huang, Atsushi Kurokawa, Masanori Hashimoto, Takashi Sato, Minglu Jiang, Yasuaki Inoue

    Research output: Contribution to journalArticle

    31 Citations (Scopus)

    Abstract

    With the scaling of complementary metal-oxide-semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacitance has more significant influence on CMOS gate analysis, especially on CMOS gate static timing analysis. In this paper, the overshooting effect is modeled for CMOS inverter delay analysis in nanometer technologies. The results produced by the proposed model are close to simulation program with integrated circuit emphasis (SPICE). Moreover, the influence of the overshooting effect on CMOS inverter analysis is discussed. An analytical model is presented to calculate the CMOS inverter delay time based on the proposed overshooting effect model, which is verified to be in good agreement with SPICE results. Furthermore, the proposed model is used to improve the accuracy of the switch-resistor model for approximating the inverter output waveform.

    Original languageEnglish
    Article number5395729
    Pages (from-to)250-260
    Number of pages11
    JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
    Volume29
    Issue number2
    DOIs
    Publication statusPublished - 2010 Feb

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    Metals
    Integrated circuits
    Resistors
    Oxide semiconductors
    Analytical models
    Time delay
    Capacitance
    Switches

    Keywords

    • CMOS inverter
    • Gate delay
    • Nanometer technology
    • Overshooting time
    • Switch-resistor model
    • Timing analysis

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Graphics and Computer-Aided Design
    • Software

    Cite this

    Modeling the overshooting effect for CMOS inverter delay analysis in nanometer technologies. / Huang, Zhangcai; Kurokawa, Atsushi; Hashimoto, Masanori; Sato, Takashi; Jiang, Minglu; Inoue, Yasuaki.

    In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No. 2, 5395729, 02.2010, p. 250-260.

    Research output: Contribution to journalArticle

    Huang, Zhangcai ; Kurokawa, Atsushi ; Hashimoto, Masanori ; Sato, Takashi ; Jiang, Minglu ; Inoue, Yasuaki. / Modeling the overshooting effect for CMOS inverter delay analysis in nanometer technologies. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2010 ; Vol. 29, No. 2. pp. 250-260.
    @article{395e6829c0764c51b23ea0eca01166f2,
    title = "Modeling the overshooting effect for CMOS inverter delay analysis in nanometer technologies",
    abstract = "With the scaling of complementary metal-oxide-semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacitance has more significant influence on CMOS gate analysis, especially on CMOS gate static timing analysis. In this paper, the overshooting effect is modeled for CMOS inverter delay analysis in nanometer technologies. The results produced by the proposed model are close to simulation program with integrated circuit emphasis (SPICE). Moreover, the influence of the overshooting effect on CMOS inverter analysis is discussed. An analytical model is presented to calculate the CMOS inverter delay time based on the proposed overshooting effect model, which is verified to be in good agreement with SPICE results. Furthermore, the proposed model is used to improve the accuracy of the switch-resistor model for approximating the inverter output waveform.",
    keywords = "CMOS inverter, Gate delay, Nanometer technology, Overshooting time, Switch-resistor model, Timing analysis",
    author = "Zhangcai Huang and Atsushi Kurokawa and Masanori Hashimoto and Takashi Sato and Minglu Jiang and Yasuaki Inoue",
    year = "2010",
    month = "2",
    doi = "10.1109/TCAD.2009.2035539",
    language = "English",
    volume = "29",
    pages = "250--260",
    journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",
    issn = "0278-0070",
    publisher = "Institute of Electrical and Electronics Engineers Inc.",
    number = "2",

    }

    TY - JOUR

    T1 - Modeling the overshooting effect for CMOS inverter delay analysis in nanometer technologies

    AU - Huang, Zhangcai

    AU - Kurokawa, Atsushi

    AU - Hashimoto, Masanori

    AU - Sato, Takashi

    AU - Jiang, Minglu

    AU - Inoue, Yasuaki

    PY - 2010/2

    Y1 - 2010/2

    N2 - With the scaling of complementary metal-oxide-semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacitance has more significant influence on CMOS gate analysis, especially on CMOS gate static timing analysis. In this paper, the overshooting effect is modeled for CMOS inverter delay analysis in nanometer technologies. The results produced by the proposed model are close to simulation program with integrated circuit emphasis (SPICE). Moreover, the influence of the overshooting effect on CMOS inverter analysis is discussed. An analytical model is presented to calculate the CMOS inverter delay time based on the proposed overshooting effect model, which is verified to be in good agreement with SPICE results. Furthermore, the proposed model is used to improve the accuracy of the switch-resistor model for approximating the inverter output waveform.

    AB - With the scaling of complementary metal-oxide-semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacitance has more significant influence on CMOS gate analysis, especially on CMOS gate static timing analysis. In this paper, the overshooting effect is modeled for CMOS inverter delay analysis in nanometer technologies. The results produced by the proposed model are close to simulation program with integrated circuit emphasis (SPICE). Moreover, the influence of the overshooting effect on CMOS inverter analysis is discussed. An analytical model is presented to calculate the CMOS inverter delay time based on the proposed overshooting effect model, which is verified to be in good agreement with SPICE results. Furthermore, the proposed model is used to improve the accuracy of the switch-resistor model for approximating the inverter output waveform.

    KW - CMOS inverter

    KW - Gate delay

    KW - Nanometer technology

    KW - Overshooting time

    KW - Switch-resistor model

    KW - Timing analysis

    UR - http://www.scopus.com/inward/record.url?scp=76649119799&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=76649119799&partnerID=8YFLogxK

    U2 - 10.1109/TCAD.2009.2035539

    DO - 10.1109/TCAD.2009.2035539

    M3 - Article

    AN - SCOPUS:76649119799

    VL - 29

    SP - 250

    EP - 260

    JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

    JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

    SN - 0278-0070

    IS - 2

    M1 - 5395729

    ER -