Modeling the overshooting effect for CMOS inverter in nanometer technologies

Huang Zhangcai, Yu Hong, Atsushi Kurokawa, Yasuaki Inoue

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    8 Citations (Scopus)

    Abstract

    With the scaling of CMOS technology, the over-shooting time due to the input-to-output coupling capacitance has much more significant effect on inverter delay. Moreover, the overshooting time is also an important parameter in the short circuit power estimation. Therefore, in this paper an effective analytical model is proposed to estimate the overshooting time for the CMOS inverter in nanometer technologies. Furthermore, the influence of process variation on the overshooting time is illustrated based on the proposed model. And the accuracy of the proposed model is proved to greatly agree with SPICE simulation results.

    Original languageEnglish
    Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
    Pages565-570
    Number of pages6
    DOIs
    Publication statusPublished - 2007
    EventASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 - Yokohama
    Duration: 2007 Jan 232007 Jan 27

    Other

    OtherASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
    CityYokohama
    Period07/1/2307/1/27

      Fingerprint

    ASJC Scopus subject areas

    • Engineering(all)

    Cite this

    Zhangcai, H., Hong, Y., Kurokawa, A., & Inoue, Y. (2007). Modeling the overshooting effect for CMOS inverter in nanometer technologies. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 565-570). [4196092] https://doi.org/10.1109/ASPDAC.2007.358046