Modeling the overshooting effect in the submicron CMOS inverters

Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The modeling of gate delays has always been one of the most difficult and market-sensitive works. In submicron designs, the second-order effects such as the input-to-output coupling capacitance have a significant influence on gate delay as shown in this paper. However, the accurate analysis of the input-to-output coupling capacitance effect has not been presented in previous research. In this paper, an analytical model for the influence of input-to-output coupling capacitance on CMOS inverter delay is proposed, in which a novel algorithm for computing overshooting time is given. Experimental results show good agreement with Spice simulations.

Original languageEnglish
Title of host publication2005 International Conference on Communications, Circuits and Systems - Proceedings
Pages1191-1195
Number of pages5
Volume2
Publication statusPublished - 2005
Externally publishedYes
Event2005 International Conference on Communications, Circuits and Systems - Hong Kong
Duration: 2005 May 272005 May 30

Other

Other2005 International Conference on Communications, Circuits and Systems
CityHong Kong
Period05/5/2705/5/30

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Huang, Z., Kurokawa, A., & Inoue, Y. (2005). Modeling the overshooting effect in the submicron CMOS inverters. In 2005 International Conference on Communications, Circuits and Systems - Proceedings (Vol. 2, pp. 1191-1195). [CAS-31.O(#08_03_05)]