Modeling the overshooting effect of multi-input gate in nanometer technologies

Li Ding, Zhangcai Huang, Minglu Jiang, Atsushi Kurokawa, Yasuaki Inoue

    Research output: Contribution to journalArticle

    1 Citation (Scopus)

    Abstract

    With the advent of nanometer age in digital circuits, the overshooting time becomes an important component of gate delay for CMOS logic gates. However, there has been little attention paid to the research of the overshooting effect for multi-input gate in nanometer technologies until now. Therefore, in this paper, an effective model considering the overshooting effect of multi-input gate is presented. The experimental results using 32-nm PTM model reflect that the proposed model is accurate within 3.6% error compared with SPICE simulation results.

    Original languageEnglish
    Article number1240012
    JournalJournal of Circuits, Systems and Computers
    Volume21
    Issue number6
    DOIs
    Publication statusPublished - 2012 Oct

    Keywords

    • gate delay
    • multi-input gate
    • Nanometer age
    • overshooting effect

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Hardware and Architecture

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