Modeling the overshooting effect of multi-input gate in nanometer technologies

Li Ding, Zhangcai Huang, Minglu Jiang, Atsushi Kurokawa, Yasuaki Inoue

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)

    Abstract

    With the advent of nanometer age in digital circuits, the overshooting time becomes a dominating component of gate delay for CMOS logic gates. Till now, few researches have focused on the overshooting effect of multi-input gate. Therefore, in this paper, an effective model considering the overshooting effect of multi-input gate is presented. The experimental results using 32nm PTM model reflect that the proposed model is accurate within 3.6% error compared with SPICE simulation results.

    Original languageEnglish
    Title of host publicationMidwest Symposium on Circuits and Systems
    DOIs
    Publication statusPublished - 2011
    Event54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 - Seoul
    Duration: 2011 Aug 72011 Aug 10

    Other

    Other54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
    CitySeoul
    Period11/8/711/8/10

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Electronic, Optical and Magnetic Materials

    Fingerprint Dive into the research topics of 'Modeling the overshooting effect of multi-input gate in nanometer technologies'. Together they form a unique fingerprint.

  • Cite this

    Ding, L., Huang, Z., Jiang, M., Kurokawa, A., & Inoue, Y. (2011). Modeling the overshooting effect of multi-input gate in nanometer technologies. In Midwest Symposium on Circuits and Systems [6026587] https://doi.org/10.1109/MWSCAS.2011.6026587