Motion compensation architecture for 8K UHDTV HEVC decoder

Shihao Wang, Dajiang Zhou, Satoshi Goto

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    9 Citations (Scopus)

    Abstract

    This paper presents a motion compensation (MC) architecture for 8K UHDTV HEVC video decoder. UHDTV's high resolution significantly increases throughput and memory traffic. Moreover, HEVC supports new coding tools like various sizes of coding unit ranging from 8 to 64. To solve these problems, we propose three optimization schemes. Firstly, four-bank parallel 2D cache organization is proposed to reduce 61.86% memory traffic and support higher interpolator throughput for HEVC. Secondly, we propose pipelined Write-Through mechanism (WTM) to achieve conflict-free performance. Moreover, WTM scheme contributes to around 50% reduction on both memory area and logic gate. Finally, highly parallel interpolator with proposed cache forms integral structure supporting UHDTV. In 90nm process, our design cost 103.6k logic gates with 12kB cache memory. The proposed architecture can support real-time decoding 7680×4320@30fps at 280MHz.

    Original languageEnglish
    Title of host publicationProceedings - IEEE International Conference on Multimedia and Expo
    PublisherIEEE Computer Society
    Volume2014-September
    EditionSeptmber
    DOIs
    Publication statusPublished - 2014 Sep 3
    Event2014 IEEE International Conference on Multimedia and Expo, ICME 2014 - Chengdu, China
    Duration: 2014 Jul 142014 Jul 18

    Other

    Other2014 IEEE International Conference on Multimedia and Expo, ICME 2014
    CountryChina
    CityChengdu
    Period14/7/1414/7/18

    Fingerprint

    Motion compensation
    Logic gates
    Data storage equipment
    Throughput
    Cache memory
    Decoding
    Costs

    Keywords

    • HEVC
    • interpolation
    • motion compensation
    • real-time decoding
    • UHDTV

    ASJC Scopus subject areas

    • Computer Networks and Communications
    • Computer Science Applications

    Cite this

    Wang, S., Zhou, D., & Goto, S. (2014). Motion compensation architecture for 8K UHDTV HEVC decoder. In Proceedings - IEEE International Conference on Multimedia and Expo (Septmber ed., Vol. 2014-September). [6890221] IEEE Computer Society. https://doi.org/10.1109/ICME.2014.6890221

    Motion compensation architecture for 8K UHDTV HEVC decoder. / Wang, Shihao; Zhou, Dajiang; Goto, Satoshi.

    Proceedings - IEEE International Conference on Multimedia and Expo. Vol. 2014-September Septmber. ed. IEEE Computer Society, 2014. 6890221.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Wang, S, Zhou, D & Goto, S 2014, Motion compensation architecture for 8K UHDTV HEVC decoder. in Proceedings - IEEE International Conference on Multimedia and Expo. Septmber edn, vol. 2014-September, 6890221, IEEE Computer Society, 2014 IEEE International Conference on Multimedia and Expo, ICME 2014, Chengdu, China, 14/7/14. https://doi.org/10.1109/ICME.2014.6890221
    Wang S, Zhou D, Goto S. Motion compensation architecture for 8K UHDTV HEVC decoder. In Proceedings - IEEE International Conference on Multimedia and Expo. Septmber ed. Vol. 2014-September. IEEE Computer Society. 2014. 6890221 https://doi.org/10.1109/ICME.2014.6890221
    Wang, Shihao ; Zhou, Dajiang ; Goto, Satoshi. / Motion compensation architecture for 8K UHDTV HEVC decoder. Proceedings - IEEE International Conference on Multimedia and Expo. Vol. 2014-September Septmber. ed. IEEE Computer Society, 2014.
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