Abstract
This paper presents a motion compensation (MC) architecture for 8K UHDTV HEVC video decoder. UHDTV's high resolution significantly increases throughput and memory traffic. Moreover, HEVC supports new coding tools like various sizes of coding unit ranging from 8 to 64. To solve these problems, we propose three optimization schemes. Firstly, four-bank parallel 2D cache organization is proposed to reduce 61.86% memory traffic and support higher interpolator throughput for HEVC. Secondly, we propose pipelined Write-Through mechanism (WTM) to achieve conflict-free performance. Moreover, WTM scheme contributes to around 50% reduction on both memory area and logic gate. Finally, highly parallel interpolator with proposed cache forms integral structure supporting UHDTV. In 90nm process, our design cost 103.6k logic gates with 12kB cache memory. The proposed architecture can support real-time decoding 7680×4320@30fps at 280MHz.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - IEEE International Conference on Multimedia and Expo |
| Publisher | IEEE Computer Society |
| Volume | 2014-September |
| Edition | Septmber |
| DOIs | |
| Publication status | Published - 2014 Sep 3 |
| Event | 2014 IEEE International Conference on Multimedia and Expo, ICME 2014 - Chengdu, China Duration: 2014 Jul 14 → 2014 Jul 18 |
Other
| Other | 2014 IEEE International Conference on Multimedia and Expo, ICME 2014 |
|---|---|
| Country | China |
| City | Chengdu |
| Period | 14/7/14 → 14/7/18 |
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Keywords
- HEVC
- interpolation
- motion compensation
- real-time decoding
- UHDTV
ASJC Scopus subject areas
- Computer Networks and Communications
- Computer Science Applications
Cite this
Motion compensation architecture for 8K UHDTV HEVC decoder. / Wang, Shihao; Zhou, Dajiang; Goto, Satoshi.
Proceedings - IEEE International Conference on Multimedia and Expo. Vol. 2014-September Septmber. ed. IEEE Computer Society, 2014. 6890221.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Motion compensation architecture for 8K UHDTV HEVC decoder
AU - Wang, Shihao
AU - Zhou, Dajiang
AU - Goto, Satoshi
PY - 2014/9/3
Y1 - 2014/9/3
N2 - This paper presents a motion compensation (MC) architecture for 8K UHDTV HEVC video decoder. UHDTV's high resolution significantly increases throughput and memory traffic. Moreover, HEVC supports new coding tools like various sizes of coding unit ranging from 8 to 64. To solve these problems, we propose three optimization schemes. Firstly, four-bank parallel 2D cache organization is proposed to reduce 61.86% memory traffic and support higher interpolator throughput for HEVC. Secondly, we propose pipelined Write-Through mechanism (WTM) to achieve conflict-free performance. Moreover, WTM scheme contributes to around 50% reduction on both memory area and logic gate. Finally, highly parallel interpolator with proposed cache forms integral structure supporting UHDTV. In 90nm process, our design cost 103.6k logic gates with 12kB cache memory. The proposed architecture can support real-time decoding 7680×4320@30fps at 280MHz.
AB - This paper presents a motion compensation (MC) architecture for 8K UHDTV HEVC video decoder. UHDTV's high resolution significantly increases throughput and memory traffic. Moreover, HEVC supports new coding tools like various sizes of coding unit ranging from 8 to 64. To solve these problems, we propose three optimization schemes. Firstly, four-bank parallel 2D cache organization is proposed to reduce 61.86% memory traffic and support higher interpolator throughput for HEVC. Secondly, we propose pipelined Write-Through mechanism (WTM) to achieve conflict-free performance. Moreover, WTM scheme contributes to around 50% reduction on both memory area and logic gate. Finally, highly parallel interpolator with proposed cache forms integral structure supporting UHDTV. In 90nm process, our design cost 103.6k logic gates with 12kB cache memory. The proposed architecture can support real-time decoding 7680×4320@30fps at 280MHz.
KW - HEVC
KW - interpolation
KW - motion compensation
KW - real-time decoding
KW - UHDTV
UR - http://www.scopus.com/inward/record.url?scp=84937459656&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84937459656&partnerID=8YFLogxK
U2 - 10.1109/ICME.2014.6890221
DO - 10.1109/ICME.2014.6890221
M3 - Conference contribution
AN - SCOPUS:84937459656
VL - 2014-September
BT - Proceedings - IEEE International Conference on Multimedia and Expo
PB - IEEE Computer Society
ER -