Multi-clock path analysis using propositional satisfiability

Kazuhiro Nakamura, Shinji Maruoka, Shinji Kimura, Katsumasa Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

We present a satisfiability based multi-clock path analysis method. The method uses propositional satisfiability (SAT) in the detection of multi-clock paths. We show a method to reduce the multi-clock path detection problems to SAT problems. We also show heuristics on the conversion from multi-level circuits into CNF formulae. We have applied our method to ISCAS89 benchmarks and other sample circuits. Experimental results show the improvement on the manipulatable size of circuits by using SAT.

Original languageEnglish
Title of host publicationProceedings of the 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000
Pages81-86
Number of pages6
DOIs
Publication statusPublished - 2000 Dec 1
Externally publishedYes
Event2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000 - Yokohama, Japan
Duration: 2000 Jan 252000 Jan 28

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000
CountryJapan
CityYokohama
Period00/1/2500/1/28

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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