Multi-clock path analysis using propositional satisfiability

Kazuhiro Nakamura, Shinji Maruoka, Shinji Kimura, Katsumasa Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

We present a satisfiability based multi-clock path analysis method. The method uses propositional satisfiability (SAT) in the detection of multi-clock paths. We show a method to reduce the multi-clock path detection problems to SAT problems. We also show heuristics on the conversion from multi-level circuits into CNF formulae. We have applied our method to ISCAS89 benchmarks and other sample circuits. Experimental results show the improvement on the manipulatable size of circuits by using SAT.

Original languageEnglish
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Pages81-86
Number of pages6
DOIs
Publication statusPublished - 2000
Externally publishedYes
Event2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000 - Yokohama
Duration: 2000 Jan 252000 Jan 28

Other

Other2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000
CityYokohama
Period00/1/2500/1/28

Fingerprint

Clocks
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

Cite this

Nakamura, K., Maruoka, S., Kimura, S., & Watanabe, K. (2000). Multi-clock path analysis using propositional satisfiability. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 81-86) https://doi.org/10.1145/368434.368533

Multi-clock path analysis using propositional satisfiability. / Nakamura, Kazuhiro; Maruoka, Shinji; Kimura, Shinji; Watanabe, Katsumasa.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2000. p. 81-86.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nakamura, K, Maruoka, S, Kimura, S & Watanabe, K 2000, Multi-clock path analysis using propositional satisfiability. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. pp. 81-86, 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000, Yokohama, 00/1/25. https://doi.org/10.1145/368434.368533
Nakamura K, Maruoka S, Kimura S, Watanabe K. Multi-clock path analysis using propositional satisfiability. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2000. p. 81-86 https://doi.org/10.1145/368434.368533
Nakamura, Kazuhiro ; Maruoka, Shinji ; Kimura, Shinji ; Watanabe, Katsumasa. / Multi-clock path analysis using propositional satisfiability. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2000. pp. 81-86
@inproceedings{5e98b5fb1baf47e8aea86b3edd832e1b,
title = "Multi-clock path analysis using propositional satisfiability",
abstract = "We present a satisfiability based multi-clock path analysis method. The method uses propositional satisfiability (SAT) in the detection of multi-clock paths. We show a method to reduce the multi-clock path detection problems to SAT problems. We also show heuristics on the conversion from multi-level circuits into CNF formulae. We have applied our method to ISCAS89 benchmarks and other sample circuits. Experimental results show the improvement on the manipulatable size of circuits by using SAT.",
author = "Kazuhiro Nakamura and Shinji Maruoka and Shinji Kimura and Katsumasa Watanabe",
year = "2000",
doi = "10.1145/368434.368533",
language = "English",
isbn = "0780359747",
pages = "81--86",
booktitle = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

}

TY - GEN

T1 - Multi-clock path analysis using propositional satisfiability

AU - Nakamura, Kazuhiro

AU - Maruoka, Shinji

AU - Kimura, Shinji

AU - Watanabe, Katsumasa

PY - 2000

Y1 - 2000

N2 - We present a satisfiability based multi-clock path analysis method. The method uses propositional satisfiability (SAT) in the detection of multi-clock paths. We show a method to reduce the multi-clock path detection problems to SAT problems. We also show heuristics on the conversion from multi-level circuits into CNF formulae. We have applied our method to ISCAS89 benchmarks and other sample circuits. Experimental results show the improvement on the manipulatable size of circuits by using SAT.

AB - We present a satisfiability based multi-clock path analysis method. The method uses propositional satisfiability (SAT) in the detection of multi-clock paths. We show a method to reduce the multi-clock path detection problems to SAT problems. We also show heuristics on the conversion from multi-level circuits into CNF formulae. We have applied our method to ISCAS89 benchmarks and other sample circuits. Experimental results show the improvement on the manipulatable size of circuits by using SAT.

UR - http://www.scopus.com/inward/record.url?scp=50249097657&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=50249097657&partnerID=8YFLogxK

U2 - 10.1145/368434.368533

DO - 10.1145/368434.368533

M3 - Conference contribution

SN - 0780359747

SN - 9780780359741

SP - 81

EP - 86

BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

ER -