Abstract
3-D (stacked device layers) ICs can significantly alleviate the interconnect problem coming with the decreasing feature size and is promising for heterogeneous integration. In this paper, we concentrate on the configuration number and fixed-outline constraints in the floorplanning for 3-D ICs. Extended sequence pair, named partitioned sequence pair (in short, P-SP), is used to represent 3-D IC floorplans. We prove that the number of configuration of 3-D IC floorplans represented by P-SP is less than that of planar floorplans represented by sequence pair (SP) and decreases as the device layer number increases. Moreover, we applied the technique of block position enumeration, which have been successfully used in planar fixed-outline floorplanning, to fixed-outline multi-layer floorplanning. The experimental results demonstrate the efficiency and effectiveness of the proposed method.
| Original language | English |
|---|---|
| Pages (from-to) | 378-388 |
| Number of pages | 11 |
| Journal | Integration, the VLSI Journal |
| Volume | 43 |
| Issue number | 4 |
| DOIs | |
| Publication status | Published - 2010 Sep |
Keywords
- 3-D ICs
- Fixed-outline
- Floorplanning
- Sequence pair
- Through silicon via (TSV)
ASJC Scopus subject areas
- Hardware and Architecture
- Software
- Electrical and Electronic Engineering
Cite this
Multi-layer floorplanning for stacked ICs : Configuration number and fixed-outline constraints. / Chen, Song; Yoshimura, Takeshi.
In: Integration, the VLSI Journal, Vol. 43, No. 4, 09.2010, p. 378-388.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Multi-layer floorplanning for stacked ICs
T2 - Configuration number and fixed-outline constraints
AU - Chen, Song
AU - Yoshimura, Takeshi
PY - 2010/9
Y1 - 2010/9
N2 - 3-D (stacked device layers) ICs can significantly alleviate the interconnect problem coming with the decreasing feature size and is promising for heterogeneous integration. In this paper, we concentrate on the configuration number and fixed-outline constraints in the floorplanning for 3-D ICs. Extended sequence pair, named partitioned sequence pair (in short, P-SP), is used to represent 3-D IC floorplans. We prove that the number of configuration of 3-D IC floorplans represented by P-SP is less than that of planar floorplans represented by sequence pair (SP) and decreases as the device layer number increases. Moreover, we applied the technique of block position enumeration, which have been successfully used in planar fixed-outline floorplanning, to fixed-outline multi-layer floorplanning. The experimental results demonstrate the efficiency and effectiveness of the proposed method.
AB - 3-D (stacked device layers) ICs can significantly alleviate the interconnect problem coming with the decreasing feature size and is promising for heterogeneous integration. In this paper, we concentrate on the configuration number and fixed-outline constraints in the floorplanning for 3-D ICs. Extended sequence pair, named partitioned sequence pair (in short, P-SP), is used to represent 3-D IC floorplans. We prove that the number of configuration of 3-D IC floorplans represented by P-SP is less than that of planar floorplans represented by sequence pair (SP) and decreases as the device layer number increases. Moreover, we applied the technique of block position enumeration, which have been successfully used in planar fixed-outline floorplanning, to fixed-outline multi-layer floorplanning. The experimental results demonstrate the efficiency and effectiveness of the proposed method.
KW - 3-D ICs
KW - Fixed-outline
KW - Floorplanning
KW - Sequence pair
KW - Through silicon via (TSV)
UR - http://www.scopus.com/inward/record.url?scp=77955851596&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77955851596&partnerID=8YFLogxK
U2 - 10.1016/j.vlsi.2010.04.001
DO - 10.1016/j.vlsi.2010.04.001
M3 - Article
AN - SCOPUS:77955851596
VL - 43
SP - 378
EP - 388
JO - Integration, the VLSI Journal
JF - Integration, the VLSI Journal
SN - 0167-9260
IS - 4
ER -