The semiconductor final testing scheduling problem (SFTSP) is a variation of the complex scheduling problem, which deals with the arrangement of the job sequence for the final testing process. In this paper, we present an actual SFTSP case includes almost all the flow-shop factors as reentry characteristic, serial and batch processing stages, lot-clusters and parallel machines. Since the critical equipment needs to be utilized efficiently at a specific testing stage, the scheduling arrangement is then playing an important role in order to reduce both the makespan and penalty cost of all late products in total final testing progress. On account of the difficulty and long time it takes to solve this problem, we propose a multi-objective optimization approach, which uses a lot-merging procedure, a new job-based encoding method, and an adjustment to the non-dominated sorting genetic algorithm II (NSGA-II). Simulation results of the adjusted NSGA-II on this SFTSP problem are compared with its traditional algorithm and much better performance of the adjusted one is observed.