Multi-operand adder synthesis targeting FPGAs

Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga

Research output: Contribution to journalArticle

10 Citations (Scopus)

Abstract

Multi-operand adders, which calculates the summation of more than two operands, usually consist of compressor trees which reduce the number of operands to two without any carry propagation, and a carrypropagate adder for the two operands in ASIC implementation. The former part is usually realized using full adders or (3;2) counters likeWallace-trees in ASIC, while adder trees or dedicated hardware are used in FPGA. In this paper, an approach to realize compression trees on FPGAs is proposed. In case of FPGA with m-input LUT, any counters with up to m inputs can be realized with one LUT per an output. Our approach utilizes generalized parallel counters (GPCs) with up to m inputs and synthesizes highperformance compressor trees by setting some intermediate height limits in the compression process like Dadda's multipliers. Experimental results show that the number of GPCs are reduced by up to 22% compared to the existing heuristic. Its effectivity on reduction of delay is also shown against existing approaches on Altera's Stratix III.

Original languageEnglish
Pages (from-to)2579-2586
Number of pages8
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE94-A
Issue number12
DOIs
Publication statusPublished - 2011 Dec

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Keywords

  • Arithmetic synthesis
  • FPGA
  • Generalized parallel counter
  • Multi-operand adder

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

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