Multi-scenario high-level synthesis for dynamic delay variation and its evaluation on FPGA platforms

    Research output: Contribution to journalLetter

    Abstract

    Multi-scenario high-level synthesis for distributed register/controller architecture has been proposed targeting static delay variation. In this paper, we extend it and propose a floorplan-driven high-level synthesis algorithm which can be applied to dynamic delay variation by effectively using an error prediction technique, where pre-error registers are introduced to local registers in every circuit block. Experimental results show that the proposed algorithm using two and three scenarios on an FPGA chip reduces the average number of required control steps by 17.6% and 25.5% on average compared to worst-case high-level synthesis at the expense of increasing lookup-tables and flip-flops. Moreover, we implement a multi-scenario elliptic-wave-filter (EWF) circuit with three scenarios synthesized by our proposed algorithm onto an FPGA chip and run it under the environment with varying supply voltages which causes dynamic delay variation. The FPGA implementation experiments also demonstrate that the EWF circuit effectively runs on the real FPGA chip. As far as we know, this is the world-first experiment where a multi-scenario circuit runs under real dynamic delay variation environment.

    Original languageEnglish
    JournalIEICE Electronics Express
    Volume13
    Issue number18
    DOIs
    Publication statusPublished - 2016

    Fingerprint

    Field programmable gate arrays (FPGA)
    registers
    platforms
    Wave filters
    Networks (circuits)
    evaluation
    chips
    synthesis
    filters
    Table lookup
    flip-flops
    Flip flop circuits
    controllers
    Experiments
    Controllers
    High level synthesis
    causes
    Electric potential
    electric potential
    predictions

    Keywords

    • Adaptive behavior
    • Distributed register/controller architecture
    • Dynamic delay variation
    • High-level synthesis

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Condensed Matter Physics
    • Electrical and Electronic Engineering

    Cite this

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    title = "Multi-scenario high-level synthesis for dynamic delay variation and its evaluation on FPGA platforms",
    abstract = "Multi-scenario high-level synthesis for distributed register/controller architecture has been proposed targeting static delay variation. In this paper, we extend it and propose a floorplan-driven high-level synthesis algorithm which can be applied to dynamic delay variation by effectively using an error prediction technique, where pre-error registers are introduced to local registers in every circuit block. Experimental results show that the proposed algorithm using two and three scenarios on an FPGA chip reduces the average number of required control steps by 17.6{\%} and 25.5{\%} on average compared to worst-case high-level synthesis at the expense of increasing lookup-tables and flip-flops. Moreover, we implement a multi-scenario elliptic-wave-filter (EWF) circuit with three scenarios synthesized by our proposed algorithm onto an FPGA chip and run it under the environment with varying supply voltages which causes dynamic delay variation. The FPGA implementation experiments also demonstrate that the EWF circuit effectively runs on the real FPGA chip. As far as we know, this is the world-first experiment where a multi-scenario circuit runs under real dynamic delay variation environment.",
    keywords = "Adaptive behavior, Distributed register/controller architecture, Dynamic delay variation, High-level synthesis",
    author = "Koki Igawa and Masao Yanagisawa and Nozomu Togawa",
    year = "2016",
    doi = "10.1587/elex.13.20160641",
    language = "English",
    volume = "13",
    journal = "IEICE Electronics Express",
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    publisher = "The Institute of Electronics, Information and Communication Engineers (IEICE)",
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    TY - JOUR

    T1 - Multi-scenario high-level synthesis for dynamic delay variation and its evaluation on FPGA platforms

    AU - Igawa, Koki

    AU - Yanagisawa, Masao

    AU - Togawa, Nozomu

    PY - 2016

    Y1 - 2016

    N2 - Multi-scenario high-level synthesis for distributed register/controller architecture has been proposed targeting static delay variation. In this paper, we extend it and propose a floorplan-driven high-level synthesis algorithm which can be applied to dynamic delay variation by effectively using an error prediction technique, where pre-error registers are introduced to local registers in every circuit block. Experimental results show that the proposed algorithm using two and three scenarios on an FPGA chip reduces the average number of required control steps by 17.6% and 25.5% on average compared to worst-case high-level synthesis at the expense of increasing lookup-tables and flip-flops. Moreover, we implement a multi-scenario elliptic-wave-filter (EWF) circuit with three scenarios synthesized by our proposed algorithm onto an FPGA chip and run it under the environment with varying supply voltages which causes dynamic delay variation. The FPGA implementation experiments also demonstrate that the EWF circuit effectively runs on the real FPGA chip. As far as we know, this is the world-first experiment where a multi-scenario circuit runs under real dynamic delay variation environment.

    AB - Multi-scenario high-level synthesis for distributed register/controller architecture has been proposed targeting static delay variation. In this paper, we extend it and propose a floorplan-driven high-level synthesis algorithm which can be applied to dynamic delay variation by effectively using an error prediction technique, where pre-error registers are introduced to local registers in every circuit block. Experimental results show that the proposed algorithm using two and three scenarios on an FPGA chip reduces the average number of required control steps by 17.6% and 25.5% on average compared to worst-case high-level synthesis at the expense of increasing lookup-tables and flip-flops. Moreover, we implement a multi-scenario elliptic-wave-filter (EWF) circuit with three scenarios synthesized by our proposed algorithm onto an FPGA chip and run it under the environment with varying supply voltages which causes dynamic delay variation. The FPGA implementation experiments also demonstrate that the EWF circuit effectively runs on the real FPGA chip. As far as we know, this is the world-first experiment where a multi-scenario circuit runs under real dynamic delay variation environment.

    KW - Adaptive behavior

    KW - Distributed register/controller architecture

    KW - Dynamic delay variation

    KW - High-level synthesis

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    SN - 1349-2543

    IS - 18

    ER -