Multigrain parallel processing on compiler cooperative OSCAR chip multiprocessor architecture

Keiji Kimura, Takeshi Kodaka, Motoki Obata, Hironori Kasahara

    Research output: Contribution to journalArticle

    3 Citations (Scopus)

    Abstract

    This paper describes multigrain parallel processing on OSCAR (Optimally SCheduled Advanced multiprocessoR) chip multiprocessor architecture. OSCAR compiler cooperative chip multiprocessor architecture aims at development of scalable, high effective performance and cost effective chip multiprocessor with ease of use by compiler supports. OSCAR chip multiprocessor architecture integrates simple single issue processors having distributed shared data memory for optimal use of data locality over different loops and fine grain data transfer and synchronization, local data memory for private data recognized by compiler, and compiler controllable data transfer unit for over-lapping data transfer to hide data transfer overhead. This OSCAR chip multiprocessor and OSCAR multigrain parallelizing compiler have been developed simultaneously. Performance of multigrain parallel processing on OSCAR chip multiprocessor architecture is evaluated using SPEC fp 2000/95 benchmark suite. When microSPARC like single issue core is used, OSCAR chip multiprocessor architecture gives us 2.36 times speedup in fpppp, 2.64 times in su2cor, 2.88 times in turb3d, 2.98 times in hydro2d, 3.84 times in tomcatv, 3.84 times in mgrid and 3.97 times in swim respectively for four processors against single processor.

    Original languageEnglish
    Pages (from-to)570-579
    Number of pages10
    JournalIEICE Transactions on Electronics
    VolumeE86-C
    Issue number4
    Publication statusPublished - 2003 Apr

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    Data transfer
    Processing
    Data storage equipment
    Lapping
    Synchronization
    Costs

    Keywords

    • Chip multiprocessor
    • Multigrain parallel processing
    • Parallelizing compiler

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Multigrain parallel processing on compiler cooperative OSCAR chip multiprocessor architecture. / Kimura, Keiji; Kodaka, Takeshi; Obata, Motoki; Kasahara, Hironori.

    In: IEICE Transactions on Electronics, Vol. E86-C, No. 4, 04.2003, p. 570-579.

    Research output: Contribution to journalArticle

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