Multiple network-on-chip model for high performance neural network

Yiping Dong, Ce Li, Zhen Lin, Takahiro Watanabe

Research output: Contribution to journalArticle

10 Citations (Scopus)

Abstract

Hardware implementation methods for Artificial Neural Network (ANN) have been researched for a long time to achieve high performance. We have proposed a Network on Chip (NoC) for ANN, and this architecture can reduce communication load and increase performance when an implemented ANN is small. In this paper, a multiple NoC models are proposed for ANN, which can implement both a small size ANN and a large size one. The simulation result shows that the proposed multiple NoC models can reduce communication load, increase system performance of connection-per-second (CPS), and reduce system running time compared with the existing hardware ANN. Furthermore, this architecture is reconfigurable and reparable. It can be used to implement different applications of ANN.

Original languageEnglish
Pages (from-to)28-36
Number of pages9
JournalJournal of Semiconductor Technology and Science
Volume10
Issue number1
Publication statusPublished - 2010 Mar

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Neural networks
Reconfigurable architectures
Communication
Network-on-chip
Computer hardware
Hardware

Keywords

  • Artificial Neural Network (ANN)
  • Connection-Per-Second (CPS)
  • High performance
  • Low communication load
  • Multiple NoC models
  • Net-work on Chip (NOC)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Multiple network-on-chip model for high performance neural network. / Dong, Yiping; Li, Ce; Lin, Zhen; Watanabe, Takahiro.

In: Journal of Semiconductor Technology and Science, Vol. 10, No. 1, 03.2010, p. 28-36.

Research output: Contribution to journalArticle

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