Multiple test set generation method for LFSR-based BIST

Youhua Shi, Zhe Zhang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

In this paper we propose a new reseeding method for LFSR-based test pattern generation suitable for circuits with random pattern resistant faults. The character of our method is that the proposed test pattern generator (TPG) can work both in normal LFSR mode, to generate pseudorandom test vectors, and in jumping mode to make the TPG jump from a state to the required state (seed of next group). Experimental results indicate that its superiority against other known reseeding techniques with respect to the length of the test sequence and the required area overhead.

Original languageEnglish
Title of host publicationProceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages863-868
Number of pages6
ISBN (Electronic)0780376595
DOIs
Publication statusPublished - 2003 Jan 1
EventAsia and South Pacific Design Automation Conference, ASP-DAC 2003 - Kitakyushu, Japan
Duration: 2003 Jan 212003 Jan 24

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2003-January

Other

OtherAsia and South Pacific Design Automation Conference, ASP-DAC 2003
CountryJapan
CityKitakyushu
Period03/1/2103/1/24

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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  • Cite this

    Shi, Y., & Zhang, Z. (2003). Multiple test set generation method for LFSR-based BIST. In Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference (pp. 863-868). [1195138] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2003-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2003.1195138