TY - GEN
T1 - Multiple test set generation method for LFSR-based BIST
AU - Shi, Youhua
AU - Zhang, Zhe
N1 - Publisher Copyright:
© 2003 IEEE.
PY - 2003
Y1 - 2003
N2 - In this paper we propose a new reseeding method for LFSR-based test pattern generation suitable for circuits with random pattern resistant faults. The character of our method is that the proposed test pattern generator (TPG) can work both in normal LFSR mode, to generate pseudorandom test vectors, and in jumping mode to make the TPG jump from a state to the required state (seed of next group). Experimental results indicate that its superiority against other known reseeding techniques with respect to the length of the test sequence and the required area overhead.
AB - In this paper we propose a new reseeding method for LFSR-based test pattern generation suitable for circuits with random pattern resistant faults. The character of our method is that the proposed test pattern generator (TPG) can work both in normal LFSR mode, to generate pseudorandom test vectors, and in jumping mode to make the TPG jump from a state to the required state (seed of next group). Experimental results indicate that its superiority against other known reseeding techniques with respect to the length of the test sequence and the required area overhead.
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U2 - 10.1109/ASPDAC.2003.1195138
DO - 10.1109/ASPDAC.2003.1195138
M3 - Conference contribution
AN - SCOPUS:51349091724
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 863
EP - 868
BT - Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - Asia and South Pacific Design Automation Conference, ASP-DAC 2003
Y2 - 21 January 2003 through 24 January 2003
ER -