TY - JOUR
T1 - NCTUcell
T2 - A DDA-and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map
AU - Li, Yih Lang
AU - Lin, Shih Ting
AU - Nishizawa, Shinichi
AU - Su, Hong Yan
AU - Fong, Ming Jie
AU - Chen, Oscar
AU - Onodera, Hidetoshi
N1 - Funding Information:
This work was supported in part by the Ministry of Science and Technology (MOST) under Grant 109-2221-E-009-109-MY2 and Grant 110-2622-8-009-006-TA.
Publisher Copyright:
© 1982-2012 IEEE.
PY - 2022/12/1
Y1 - 2022/12/1
N2 - For the 7-nm technology node, cell placement with a drain-to-drain abutment (DDA) requires additional filler cells, increasing the placement area. This is the first work to fully automatically synthesize a DDA-aware cell library with the optimized number of drains on cell boundary based on ASAP 7-nm PDK. We propose a DDA-aware dynamic programming-based transistor placement. Previous works ignore the use of the M0 layer in cell routing. We first propose an ILP-based M0 routing planning. With M0 routing, the congestion of M1 routing can be reduced and the pin accessibility (PA) can be improved due to the diminished use of M2 routing. We also present a quadratic-programming based-coupling-capacitance-aware initial routing to optimize cell delay, cell area, and M2 usage. To improve the routing resource utilization, we propose an implicitly adjustable grid map, making the maze routing able to explore more routing solutions. The experimental results show that block placement using the DDA-aware cell library requires fewer filler cells than that using the traditional cell library by 25.1%, which achieves a block area reduction rate of 0.97%.
AB - For the 7-nm technology node, cell placement with a drain-to-drain abutment (DDA) requires additional filler cells, increasing the placement area. This is the first work to fully automatically synthesize a DDA-aware cell library with the optimized number of drains on cell boundary based on ASAP 7-nm PDK. We propose a DDA-aware dynamic programming-based transistor placement. Previous works ignore the use of the M0 layer in cell routing. We first propose an ILP-based M0 routing planning. With M0 routing, the congestion of M1 routing can be reduced and the pin accessibility (PA) can be improved due to the diminished use of M2 routing. We also present a quadratic-programming based-coupling-capacitance-aware initial routing to optimize cell delay, cell area, and M2 usage. To improve the routing resource utilization, we propose an implicitly adjustable grid map, making the maze routing able to explore more routing solutions. The experimental results show that block placement using the DDA-aware cell library requires fewer filler cells than that using the traditional cell library by 25.1%, which achieves a block area reduction rate of 0.97%.
KW - Cell synthesis
KW - coupling capacitance
KW - drain-to-drain abutment (DDA)
KW - routing
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U2 - 10.1109/TCAD.2022.3167339
DO - 10.1109/TCAD.2022.3167339
M3 - Article
AN - SCOPUS:85128596661
VL - 41
SP - 5568
EP - 5581
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SN - 0278-0070
IS - 12
ER -