Near fine grain parallel processing using static scheduling on single chip multiprocessors

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    6 Citations (Scopus)

    Abstract

    With the increase of the number of transistors integrated on a chip, efficient use of transistors and scalable improvement of effective performance of a processor are getting im-portant problems. However, it has been thought that popular superscalar and VLIW would have difficulty to obtain scalable improvement of effective performance in future because of the limitation of instruction level parallelism. To cope with this problem, a single chip multiprocessor (SCM) approach with multi grain parallel processing inside a chip, which hierarchically exploits loop parallelism and coarse grain parallelism among subroutines, loops and basic blocks in addition to instruction level parallelism, is thought one of the most promising approaches. This paper evaluates effectiveness of the single chip multiprocessor architectures with a shared cache, global registers, distributed shared memory and/or local memory for near fine grain parallel processing as the first step of research on SCM architecture to support multi grain parallel processing. The evaluation shows OSCAR (Optimally Scheduled Advanced Multiprocessor) architecture having distributed shared memory and local memory in addition to centralized shared memory and attachment of global register gives us significant speed up such as 13.8% to 143.8% for four pro-cessors compared with shared cache architecture for applications which have been difficult to extract parallelism effectively.

    Original languageEnglish
    Title of host publicationInnovative Architecture for Future Generation High-Performance Processors and Systems - 1999 International Workshop on Innovative Architectures, IWIA 1999
    PublisherIEEE Computer Society
    Pages23-31
    Number of pages9
    Volume1999-November
    ISBN (Electronic)076950650X, 9780769506500
    DOIs
    Publication statusPublished - 1999 Jan 1
    Event1999 International Workshop on Innovative Architectures, IWIA 1999 - Maui, United States
    Duration: 1999 Nov 11999 Nov 3

    Other

    Other1999 International Workshop on Innovative Architectures, IWIA 1999
    CountryUnited States
    CityMaui
    Period99/11/199/11/3

    Fingerprint

    Scheduling
    Data storage equipment
    Processing
    Transistors
    Subroutines

    ASJC Scopus subject areas

    • Hardware and Architecture

    Cite this

    Kimura, K., & Kasahara, H. (1999). Near fine grain parallel processing using static scheduling on single chip multiprocessors. In Innovative Architecture for Future Generation High-Performance Processors and Systems - 1999 International Workshop on Innovative Architectures, IWIA 1999 (Vol. 1999-November, pp. 23-31). [898840] IEEE Computer Society. https://doi.org/10.1109/IWIA.1999.898840

    Near fine grain parallel processing using static scheduling on single chip multiprocessors. / Kimura, Keiji; Kasahara, Hironori.

    Innovative Architecture for Future Generation High-Performance Processors and Systems - 1999 International Workshop on Innovative Architectures, IWIA 1999. Vol. 1999-November IEEE Computer Society, 1999. p. 23-31 898840.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Kimura, K & Kasahara, H 1999, Near fine grain parallel processing using static scheduling on single chip multiprocessors. in Innovative Architecture for Future Generation High-Performance Processors and Systems - 1999 International Workshop on Innovative Architectures, IWIA 1999. vol. 1999-November, 898840, IEEE Computer Society, pp. 23-31, 1999 International Workshop on Innovative Architectures, IWIA 1999, Maui, United States, 99/11/1. https://doi.org/10.1109/IWIA.1999.898840
    Kimura K, Kasahara H. Near fine grain parallel processing using static scheduling on single chip multiprocessors. In Innovative Architecture for Future Generation High-Performance Processors and Systems - 1999 International Workshop on Innovative Architectures, IWIA 1999. Vol. 1999-November. IEEE Computer Society. 1999. p. 23-31. 898840 https://doi.org/10.1109/IWIA.1999.898840
    Kimura, Keiji ; Kasahara, Hironori. / Near fine grain parallel processing using static scheduling on single chip multiprocessors. Innovative Architecture for Future Generation High-Performance Processors and Systems - 1999 International Workshop on Innovative Architectures, IWIA 1999. Vol. 1999-November IEEE Computer Society, 1999. pp. 23-31
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