Network flow-based simultaneous retiming and slack budgeting for low power design

Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Low power design has become one of the most significant requirements when CMOS technology entered the nanometer era. Therefore, timing budget is often performed to slow down as many components as possible so that timing slacks can be applied to reduce the power consumption while maintaining the performance of the whole design. Retiming is a procedure that involves the relocation of flip-flops (FFs) across logic gates to achieve faster clocking speed. In this paper we show that the retiming and slack budgeting problem can be formulated to a convex cost dual network flow problem. Both the theoretical analysis and experimental results show the efficiency of our approach which can not only reduce power consumption by 8.9%, but also speedup previous work by 500 times.

Original languageEnglish
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Pages473-478
Number of pages6
DOIs
Publication statusPublished - 2011
Event2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011 - Yokohama
Duration: 2011 Jan 252011 Jan 28

Other

Other2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011
CityYokohama
Period11/1/2511/1/28

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

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  • Cite this

    Yu, B., Dong, S., Ma, Y., Lin, T., Wang, Y., Chen, S., & Goto, S. (2011). Network flow-based simultaneous retiming and slack budgeting for low power design. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 473-478). [5722236] https://doi.org/10.1109/ASPDAC.2011.5722236