Network on chip architecture for BP neural network

Yiping Dong*, Takahiro Watanabe

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

Recently, Networks-on-Chips (NoCs) have a great development and have been proposed as a promising solution to complex on-chip communication problems. One of the problems is an application of Artificial Neural Networks (ANNs). In this paper, we propose NoCs for the ANNs. NoCs is designed to implement a BP-ANNs (Back-Propagation) and evaluated by Network-on-Chips. Experimental results show that for has a great reduction in communication load and a high connection per second (CPS) compared with traditional BP-ANNs. It is also reconfigurable, expandable and stable to meet various problems.

Original languageEnglish
Title of host publication2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008
Pages964-968
Number of pages5
DOIs
Publication statusPublished - 2008
Externally publishedYes
Event2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008 - Xiamen, Fujian Province, China
Duration: 2008 May 252008 May 27

Publication series

Name2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008

Conference

Conference2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008
Country/TerritoryChina
CityXiamen, Fujian Province
Period08/5/2508/5/27

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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