Network on chip architecture for BP neural network

Yiping Dong, Takahiro Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

Recently, Networks-on-Chips (NoCs) have a great development and have been proposed as a promising solution to complex on-chip communication problems. One of the problems is an application of Artificial Neural Networks (ANNs). In this paper, we propose NoCs for the ANNs. NoCs is designed to implement a BP-ANNs (Back-Propagation) and evaluated by Network-on-Chips. Experimental results show that for has a great reduction in communication load and a high connection per second (CPS) compared with traditional BP-ANNs. It is also reconfigurable, expandable and stable to meet various problems.

Original languageEnglish
Title of host publication2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008
Pages964-968
Number of pages5
DOIs
Publication statusPublished - 2008
Event2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008 - Xiamen, Fujian Province
Duration: 2008 May 252008 May 27

Other

Other2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008
CityXiamen, Fujian Province
Period08/5/2508/5/27

Fingerprint

Neural networks
Communication
Backpropagation
Network-on-chip

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Dong, Y., & Watanabe, T. (2008). Network on chip architecture for BP neural network. In 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008 (pp. 964-968). [4657930] https://doi.org/10.1109/ICCCAS.2008.4657930

Network on chip architecture for BP neural network. / Dong, Yiping; Watanabe, Takahiro.

2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008. 2008. p. 964-968 4657930.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Dong, Y & Watanabe, T 2008, Network on chip architecture for BP neural network. in 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008., 4657930, pp. 964-968, 2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008, Xiamen, Fujian Province, 08/5/25. https://doi.org/10.1109/ICCCAS.2008.4657930
Dong Y, Watanabe T. Network on chip architecture for BP neural network. In 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008. 2008. p. 964-968. 4657930 https://doi.org/10.1109/ICCCAS.2008.4657930
Dong, Yiping ; Watanabe, Takahiro. / Network on chip architecture for BP neural network. 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008. 2008. pp. 964-968
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