Abstract
To overcome faults in mesh-connected processor arrays, a number of reconfiguration schemes have been studied in the literature. As one of them, the mesh-connected processor arrays model based on single-track switches has been proposed in [1]. The model has an advantage of its inherent simplicity of the routing hardware. So far, some algorithms have been proposed to solve the problem of reconfiguration for this model. In [2], a polynomial time algorithm has been presented. However, it needs a global information on fault distribution and it seems to be a troublesome job to implement the algorithm even by software while it may be impossible to implement it by hardware. In this paper, using Hopfield-type neural network model, we present an algorithm for reconstructing the mesh-connected processor arrays using single-track switches and show its effectiveness by computer simulation. Furthermore, we present a hardware implementation of the neural algorithm by which a self-repair system can be realized.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon |
| Editors | Stuart Tewkbury, Glenn Chapman |
| Publisher | IEEE |
| Pages | 101-110 |
| Number of pages | 10 |
| Publication status | Published - 1995 |
| Externally published | Yes |
| Event | Proceedings of the 7th Annual IEEE International Conference on Wafer Scale Integration - San Francisco, CA, USA Duration: 1995 Jan 18 → 1995 Jan 20 |
Other
| Other | Proceedings of the 7th Annual IEEE International Conference on Wafer Scale Integration |
|---|---|
| City | San Francisco, CA, USA |
| Period | 95/1/18 → 95/1/20 |
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ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
- Condensed Matter Physics
Cite this
Neural algorithm for reconstructing mesh-connected processor arrays using single-track switches. / Takanami, Itsuo; Kurata, Kazushi; Watanabe, Takahiro.
Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon. ed. / Stuart Tewkbury; Glenn Chapman. IEEE, 1995. p. 101-110.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Neural algorithm for reconstructing mesh-connected processor arrays using single-track switches
AU - Takanami, Itsuo
AU - Kurata, Kazushi
AU - Watanabe, Takahiro
PY - 1995
Y1 - 1995
N2 - To overcome faults in mesh-connected processor arrays, a number of reconfiguration schemes have been studied in the literature. As one of them, the mesh-connected processor arrays model based on single-track switches has been proposed in [1]. The model has an advantage of its inherent simplicity of the routing hardware. So far, some algorithms have been proposed to solve the problem of reconfiguration for this model. In [2], a polynomial time algorithm has been presented. However, it needs a global information on fault distribution and it seems to be a troublesome job to implement the algorithm even by software while it may be impossible to implement it by hardware. In this paper, using Hopfield-type neural network model, we present an algorithm for reconstructing the mesh-connected processor arrays using single-track switches and show its effectiveness by computer simulation. Furthermore, we present a hardware implementation of the neural algorithm by which a self-repair system can be realized.
AB - To overcome faults in mesh-connected processor arrays, a number of reconfiguration schemes have been studied in the literature. As one of them, the mesh-connected processor arrays model based on single-track switches has been proposed in [1]. The model has an advantage of its inherent simplicity of the routing hardware. So far, some algorithms have been proposed to solve the problem of reconfiguration for this model. In [2], a polynomial time algorithm has been presented. However, it needs a global information on fault distribution and it seems to be a troublesome job to implement the algorithm even by software while it may be impossible to implement it by hardware. In this paper, using Hopfield-type neural network model, we present an algorithm for reconstructing the mesh-connected processor arrays using single-track switches and show its effectiveness by computer simulation. Furthermore, we present a hardware implementation of the neural algorithm by which a self-repair system can be realized.
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UR - http://www.scopus.com/inward/citedby.url?scp=0029235214&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0029235214
SP - 101
EP - 110
BT - Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon
A2 - Tewkbury, Stuart
A2 - Chapman, Glenn
PB - IEEE
ER -