Neural algorithm for reconstructing mesh-connected processor arrays using single-track switches

Itsuo Takanami, Kazushi Kurata, Takahiro Watanabe

Research output: Contribution to journalConference article

15 Citations (Scopus)


To overcome faults in mesh-connected processor arrays, a number of reconfiguration schemes have been studied in the literature. As one of them, the mesh-connected processor arrays model based on single-track switches has been proposed in [1]. The model has an advantage of its inherent simplicity of the routing hardware. So far, some algorithms have been proposed to solve the problem of reconfiguration for this model. In [2], a polynomial time algorithm has been presented. However, it needs a global information on fault distribution and it seems to be a troublesome job to implement the algorithm even by software while it may be impossible to implement it by hardware. In this paper, using Hopfield-type neural network model, we present an algorithm for reconstructing the mesh-connected processor arrays using single-track switches and show its effectiveness by computer simulation. Furthermore, we present a hardware implementation of the neural algorithm by which a self-repair system can be realized.

Original languageEnglish
Pages (from-to)101-110
Number of pages10
JournalProceedings of the Annual IEEE International Conference on Innovative Systems in Silicon
Publication statusPublished - 1995 Jan 1
EventProceedings of the 7th Annual IEEE International Conference on Wafer Scale Integration - San Francisco, CA, USA
Duration: 1995 Jan 181995 Jan 20


ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Condensed Matter Physics

Cite this