Neural algorithm for reconstructing mesh-connected processor arrays using single-track switches

Itsuo Takanami, Kazushi Kurata, Takahiro Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Abstract

To overcome faults in mesh-connected processor arrays, a number of reconfiguration schemes have been studied in the literature. As one of them, the mesh-connected processor arrays model based on single-track switches has been proposed in [1]. The model has an advantage of its inherent simplicity of the routing hardware. So far, some algorithms have been proposed to solve the problem of reconfiguration for this model. In [2], a polynomial time algorithm has been presented. However, it needs a global information on fault distribution and it seems to be a troublesome job to implement the algorithm even by software while it may be impossible to implement it by hardware. In this paper, using Hopfield-type neural network model, we present an algorithm for reconstructing the mesh-connected processor arrays using single-track switches and show its effectiveness by computer simulation. Furthermore, we present a hardware implementation of the neural algorithm by which a self-repair system can be realized.

Original languageEnglish
Title of host publicationProceedings of the Annual IEEE International Conference on Innovative Systems in Silicon
EditorsStuart Tewkbury, Glenn Chapman
PublisherIEEE
Pages101-110
Number of pages10
Publication statusPublished - 1995
Externally publishedYes
EventProceedings of the 7th Annual IEEE International Conference on Wafer Scale Integration - San Francisco, CA, USA
Duration: 1995 Jan 181995 Jan 20

Other

OtherProceedings of the 7th Annual IEEE International Conference on Wafer Scale Integration
CitySan Francisco, CA, USA
Period95/1/1895/1/20

Fingerprint

Parallel processing systems
central processing units
mesh
switches
hardware
Hardware
Computer hardware
polynomials
Repair
computerized simulation
Polynomials
Neural networks
computer programs
Computer simulation

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Condensed Matter Physics

Cite this

Takanami, I., Kurata, K., & Watanabe, T. (1995). Neural algorithm for reconstructing mesh-connected processor arrays using single-track switches. In S. Tewkbury, & G. Chapman (Eds.), Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon (pp. 101-110). IEEE.

Neural algorithm for reconstructing mesh-connected processor arrays using single-track switches. / Takanami, Itsuo; Kurata, Kazushi; Watanabe, Takahiro.

Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon. ed. / Stuart Tewkbury; Glenn Chapman. IEEE, 1995. p. 101-110.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Takanami, I, Kurata, K & Watanabe, T 1995, Neural algorithm for reconstructing mesh-connected processor arrays using single-track switches. in S Tewkbury & G Chapman (eds), Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon. IEEE, pp. 101-110, Proceedings of the 7th Annual IEEE International Conference on Wafer Scale Integration, San Francisco, CA, USA, 95/1/18.
Takanami I, Kurata K, Watanabe T. Neural algorithm for reconstructing mesh-connected processor arrays using single-track switches. In Tewkbury S, Chapman G, editors, Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon. IEEE. 1995. p. 101-110
Takanami, Itsuo ; Kurata, Kazushi ; Watanabe, Takahiro. / Neural algorithm for reconstructing mesh-connected processor arrays using single-track switches. Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon. editor / Stuart Tewkbury ; Glenn Chapman. IEEE, 1995. pp. 101-110
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