NEW ARCHITECTURE FOR THE NVRAM - AN EEPROM BACKED - UP DYNAMIC RAM.

Yasushi Terada; Kazuo Kobayashi; Takeshi Nakayama; Hideaki Arima; Tsutomu Yoshihara

NEW ARCHITECTURE FOR THE NVRAM - AN EEPROM BACKED - UP DYNAMIC RAM.

Yasushi Terada^*, Kazuo Kobayashi, Takeshi Nakayama, Hideaki Arima, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

Abstract

An architecture for a nonvolatile RAM (NVRAM) suitable for high-density applications is described. In the cell, a dynamic RAM cell is merged into an EEPROM cell. A capacitor is constructed between the control gate and the drain diffusion layer of the FLOTOX-type EEPROM memory cell. The equivalent circuit in the dynamic RAM mode consists of two transistors and a capacitor, which eliminates a dummy cell. A dynamic RAM sense amplifier is used in both modes, and it works as a data latch when data are transferred between the dynamic RAM and the EEPROM. The process of the NVRAM is compatible with ordinary EEPROMs.

Original language	English
Journal	IEEE Journal of Solid-State Circuits
Volume	23
Issue number	1
Publication status	Published - 1987 Feb
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

@article{41eab603dc49497bad125fb449f41a5a,

title = "NEW ARCHITECTURE FOR THE NVRAM - AN EEPROM BACKED - UP DYNAMIC RAM.",

abstract = "An architecture for a nonvolatile RAM (NVRAM) suitable for high-density applications is described. In the cell, a dynamic RAM cell is merged into an EEPROM cell. A capacitor is constructed between the control gate and the drain diffusion layer of the FLOTOX-type EEPROM memory cell. The equivalent circuit in the dynamic RAM mode consists of two transistors and a capacitor, which eliminates a dummy cell. A dynamic RAM sense amplifier is used in both modes, and it works as a data latch when data are transferred between the dynamic RAM and the EEPROM. The process of the NVRAM is compatible with ordinary EEPROMs.",

author = "Yasushi Terada and Kazuo Kobayashi and Takeshi Nakayama and Hideaki Arima and Tsutomu Yoshihara",

year = "1987",

month = feb,

language = "English",

volume = "23",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "1",

}

TY - JOUR

T1 - NEW ARCHITECTURE FOR THE NVRAM - AN EEPROM BACKED - UP DYNAMIC RAM.

AU - Terada, Yasushi

AU - Kobayashi, Kazuo

AU - Nakayama, Takeshi

AU - Arima, Hideaki

AU - Yoshihara, Tsutomu

PY - 1987/2

Y1 - 1987/2

N2 - An architecture for a nonvolatile RAM (NVRAM) suitable for high-density applications is described. In the cell, a dynamic RAM cell is merged into an EEPROM cell. A capacitor is constructed between the control gate and the drain diffusion layer of the FLOTOX-type EEPROM memory cell. The equivalent circuit in the dynamic RAM mode consists of two transistors and a capacitor, which eliminates a dummy cell. A dynamic RAM sense amplifier is used in both modes, and it works as a data latch when data are transferred between the dynamic RAM and the EEPROM. The process of the NVRAM is compatible with ordinary EEPROMs.

AB - An architecture for a nonvolatile RAM (NVRAM) suitable for high-density applications is described. In the cell, a dynamic RAM cell is merged into an EEPROM cell. A capacitor is constructed between the control gate and the drain diffusion layer of the FLOTOX-type EEPROM memory cell. The equivalent circuit in the dynamic RAM mode consists of two transistors and a capacitor, which eliminates a dummy cell. A dynamic RAM sense amplifier is used in both modes, and it works as a data latch when data are transferred between the dynamic RAM and the EEPROM. The process of the NVRAM is compatible with ordinary EEPROMs.

UR - http://www.scopus.com/inward/record.url?scp=0023291361&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0023291361&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0023291361

VL - 23

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 1

ER -

NEW ARCHITECTURE FOR THE NVRAM - AN EEPROM BACKED - UP DYNAMIC RAM.

Abstract

ASJC Scopus subject areas

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