Abstract
An architecture for a nonvolatile RAM (NVRAM) suitable for high-density applications is described. In the cell, a dynamic RAM cell is merged into an EEPROM cell. A capacitor is constructed between the control gate and the drain diffusion layer of the FLOTOX-type EEPROM memory cell. The equivalent circuit in the dynamic RAM mode consists of two transistors and a capacitor, which eliminates a dummy cell. A dynamic RAM sense amplifier is used in both modes, and it works as a data latch when data are transferred between the dynamic RAM and the EEPROM. The process of the NVRAM is compatible with ordinary EEPROMs.
| Original language | English |
|---|---|
| Journal | IEEE Journal of Solid-State Circuits |
| Volume | 23 |
| Issue number | 1 |
| Publication status | Published - 1987 Feb |
| Externally published | Yes |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
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Cite this
Terada, Y., Kobayashi, K., Nakayama, T., Arima, H., & Yoshihara, T. (1987). NEW ARCHITECTURE FOR THE NVRAM - AN EEPROM BACKED - UP DYNAMIC RAM. IEEE Journal of Solid-State Circuits, 23(1).