New architecture of signature analyzers for multiple-output circuits

Tomoko K. Matsushima, Toshiyasu Matsushima, Shigeichi Hirasawa

Research output: Contribution to journalConference article

5 Citations (Scopus)

Abstract

This paper presents a new architecture for multiple-input signature analyzers. The proposed signature analyzer with Hδ inputs is designed by parallelizing a GLFSR(δ, m), where δ is the number of input signals and m is the number of stages in the feedback shift register. The GLFSR, developed by Pradhan and Gupta, is a general framework for representing LFSR-based signature analyzers. The parallelization technique described in this paper can be applied to any kind of GLFSR signature analyzer, e.g., SISRs, MISRs, multiple MISRs and MLFSRs. It is shown that a proposed signature analyzer with Hδ inputs requires less complex hardware than either single GLFSR(Hδ, m)s or parallel construction H original GLFSR(δ, m)s. It is also shown that the proposed parallelization technique can be applied to a test pattern generator in BIST, since the GLFSR is also used to generate patterns for a CUT. The proposed technique would be practical for testing CUTs with a large number of input and output sequences, since the test circuit occupies a smaller area on the LSI chip than conventional test circuits.

Original languageEnglish
Pages (from-to)3900-3905
Number of pages6
JournalProceedings of the IEEE International Conference on Systems, Man and Cybernetics
Volume4
Publication statusPublished - 1997 Dec 1
EventProceedings of the 1997 IEEE International Conference on Systems, Man, and Cybernetics. Part 3 (of 5) - Orlando, FL, USA
Duration: 1997 Oct 121997 Oct 15

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ASJC Scopus subject areas

  • Control and Systems Engineering
  • Hardware and Architecture

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