Abstract
A scalabale pedestal cell technology has been successfully developed for the BST capacitor by introducing the damascene scheme into the pedestal electrode formation and by employing [Pt-Ir] alloy for coating the pedestal electrode. With a PVD-BST liner as the blanket nucleating layer and as the barrier layer against the destructive oxidant, the MOCVD-BST functions in prime condition on the storage node developed.
| Original language | English |
|---|---|
| Pages (from-to) | 106-107 |
| Number of pages | 2 |
| Journal | Digest of Technical Papers - Symposium on VLSI Technology |
| Publication status | Published - 2000 Jan 1 |
| Externally published | Yes |
| Event | 2000 Symposium on VLSI Technology - Honolulu, HI, USA Duration: 2000 Jun 13 → 2000 Jun 15 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
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Cite this
Itoh, H., Tsunemine, Y., Yutani, A., Okudaira, T., Kashihara, K., Inuishi, M., Yamamuka, M., Kawahara, T., Horikawa, T., Ohmori, T., & Satoh, S. (2000). New cell technology for the scalable BST capacitor using damascene-formed pedestal electrode with a [Pt-Ir] alloy coating. Digest of Technical Papers - Symposium on VLSI Technology, 106-107.