New cell technology for the scalable BST capacitor using damascene-formed pedestal electrode with a [Pt-Ir] alloy coating

H. Itoh; Y. Tsunemine; A. Yutani; T. Okudaira; K. Kashihara; M. Inuishi; M. Yamamuka; T. Kawahara; T. Horikawa; T. Ohmori; S. Satoh

New cell technology for the scalable BST capacitor using damascene-formed pedestal electrode with a [Pt-Ir] alloy coating

H. Itoh^*, Y. Tsunemine, A. Yutani, T. Okudaira, K. Kashihara, M. Inuishi, M. Yamamuka, T. Kawahara, T. Horikawa, T. Ohmori, S. Satoh

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

4 Citations (Scopus)

Abstract

A scalabale pedestal cell technology has been successfully developed for the BST capacitor by introducing the damascene scheme into the pedestal electrode formation and by employing [Pt-Ir] alloy for coating the pedestal electrode. With a PVD-BST liner as the blanket nucleating layer and as the barrier layer against the destructive oxidant, the MOCVD-BST functions in prime condition on the storage node developed.

Original language	English
Pages (from-to)	106-107
Number of pages	2
Journal	Digest of Technical Papers - Symposium on VLSI Technology
Publication status	Published - 2000
Externally published	Yes
Event	2000 Symposium on VLSI Technology - Honolulu, HI, USA Duration: 2000 Jun 13 → 2000 Jun 15

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

@article{723bd209589e4f04aead92abde59884e,

title = "New cell technology for the scalable BST capacitor using damascene-formed pedestal electrode with a [Pt-Ir] alloy coating",

abstract = "A scalabale pedestal cell technology has been successfully developed for the BST capacitor by introducing the damascene scheme into the pedestal electrode formation and by employing [Pt-Ir] alloy for coating the pedestal electrode. With a PVD-BST liner as the blanket nucleating layer and as the barrier layer against the destructive oxidant, the MOCVD-BST functions in prime condition on the storage node developed.",

author = "H. Itoh and Y. Tsunemine and A. Yutani and T. Okudaira and K. Kashihara and M. Inuishi and M. Yamamuka and T. Kawahara and T. Horikawa and T. Ohmori and S. Satoh",

year = "2000",

language = "English",

pages = "106--107",

journal = "Digest of Technical Papers - Symposium on VLSI Technology",

issn = "0743-1562",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2000 Symposium on VLSI Technology ; Conference date: 13-06-2000 Through 15-06-2000",

}

TY - JOUR

T1 - New cell technology for the scalable BST capacitor using damascene-formed pedestal electrode with a [Pt-Ir] alloy coating

AU - Itoh, H.

AU - Tsunemine, Y.

AU - Yutani, A.

AU - Okudaira, T.

AU - Kashihara, K.

AU - Inuishi, M.

AU - Yamamuka, M.

AU - Kawahara, T.

AU - Horikawa, T.

AU - Ohmori, T.

AU - Satoh, S.

PY - 2000

Y1 - 2000

N2 - A scalabale pedestal cell technology has been successfully developed for the BST capacitor by introducing the damascene scheme into the pedestal electrode formation and by employing [Pt-Ir] alloy for coating the pedestal electrode. With a PVD-BST liner as the blanket nucleating layer and as the barrier layer against the destructive oxidant, the MOCVD-BST functions in prime condition on the storage node developed.

AB - A scalabale pedestal cell technology has been successfully developed for the BST capacitor by introducing the damascene scheme into the pedestal electrode formation and by employing [Pt-Ir] alloy for coating the pedestal electrode. With a PVD-BST liner as the blanket nucleating layer and as the barrier layer against the destructive oxidant, the MOCVD-BST functions in prime condition on the storage node developed.

UR - http://www.scopus.com/inward/record.url?scp=0033683019&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033683019&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0033683019

SP - 106

EP - 107

JO - Digest of Technical Papers - Symposium on VLSI Technology

JF - Digest of Technical Papers - Symposium on VLSI Technology

SN - 0743-1562

T2 - 2000 Symposium on VLSI Technology

Y2 - 13 June 2000 through 15 June 2000

ER -

New cell technology for the scalable BST capacitor using damascene-formed pedestal electrode with a [Pt-Ir] alloy coating

Abstract

ASJC Scopus subject areas

Other files and links

Fingerprint

Cite this