Abstract
A CR-delay circuit technology for the realization of high-speed operation with a wide operational margin and minimized timing loss is discussed. It was applied to a 4-Mb CMOS DRAM, and the experimental results are described. A significant reduction in access time and cycle time was achieved.
| Original language | English |
|---|---|
| Title of host publication | 1988 Symp VLSI Circuits Dig Tech Pap |
| Editors | Anon |
| Pages | 75-76 |
| Number of pages | 2 |
| Publication status | Published - 1988 |
| Externally published | Yes |
| Event | 1988 Symposium on VLSI Circuits - Digest of Technical Papers - Tokyo, Japan Duration: 1988 Aug 22 → 1988 Aug 24 |
Other
| Other | 1988 Symposium on VLSI Circuits - Digest of Technical Papers |
|---|---|
| City | Tokyo, Japan |
| Period | 88/8/22 → 88/8/24 |
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ASJC Scopus subject areas
- Engineering(all)
Cite this
Watanabe, Y., Ohsawa, T., Sakurai, K., & Furuyama, T. (1988). New CR-delay circuit technology for high-density and high-speed DRAMs. In Anon (Ed.), 1988 Symp VLSI Circuits Dig Tech Pap (pp. 75-76)