New CR-delay circuit technology for high-density and high-speed DRAMs

Yohji Watanabe, Takashi Ohsawa, Kiyofumi Sakurai, Tohru Furuyama

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Abstract

A CR-delay circuit technology for the realization of high-speed operation with a wide operational margin and minimized timing loss is discussed. It was applied to a 4-Mb CMOS DRAM, and the experimental results are described. A significant reduction in access time and cycle time was achieved.

Original languageEnglish
Pages75-76
Number of pages2
Publication statusPublished - 1988 Dec 1
Externally publishedYes
Event1988 Symposium on VLSI Circuits - Digest of Technical Papers - Tokyo, Japan
Duration: 1988 Aug 221988 Aug 24

Other

Other1988 Symposium on VLSI Circuits - Digest of Technical Papers
CityTokyo, Japan
Period88/8/2288/8/24

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Watanabe, Y., Ohsawa, T., Sakurai, K., & Furuyama, T. (1988). New CR-delay circuit technology for high-density and high-speed DRAMs. 75-76. Paper presented at 1988 Symposium on VLSI Circuits - Digest of Technical Papers, Tokyo, Japan, .