New CR-delay circuit technology for high-density and high-speed DRAMs

Yohji Watanabe; Takashi Ohsawa; Kiyofumi Sakurai; Tohru Furuyama

New CR-delay circuit technology for high-density and high-speed DRAMs

Yohji Watanabe, Takashi Ohsawa, Kiyofumi Sakurai, Tohru Furuyama

Research output: Contribution to conference › Paper › peer-review

Abstract

A CR-delay circuit technology for the realization of high-speed operation with a wide operational margin and minimized timing loss is discussed. It was applied to a 4-Mb CMOS DRAM, and the experimental results are described. A significant reduction in access time and cycle time was achieved.

Original language	English
Pages	75-76
Number of pages	2
Publication status	Published - 1988 Dec 1
Externally published	Yes
Event	1988 Symposium on VLSI Circuits - Digest of Technical Papers - Tokyo, Japan Duration: 1988 Aug 22 → 1988 Aug 24

Other

Other	1988 Symposium on VLSI Circuits - Digest of Technical Papers
City	Tokyo, Japan
Period	88/8/22 → 88/8/24

ASJC Scopus subject areas

Engineering(all)

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Cite this

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title = "New CR-delay circuit technology for high-density and high-speed DRAMs",

abstract = "A CR-delay circuit technology for the realization of high-speed operation with a wide operational margin and minimized timing loss is discussed. It was applied to a 4-Mb CMOS DRAM, and the experimental results are described. A significant reduction in access time and cycle time was achieved.",

author = "Yohji Watanabe and Takashi Ohsawa and Kiyofumi Sakurai and Tohru Furuyama",

year = "1988",

month = dec,

day = "1",

language = "English",

pages = "75--76",

note = "1988 Symposium on VLSI Circuits - Digest of Technical Papers ; Conference date: 22-08-1988 Through 24-08-1988",

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TY - CONF

T1 - New CR-delay circuit technology for high-density and high-speed DRAMs

AU - Watanabe, Yohji

AU - Ohsawa, Takashi

AU - Sakurai, Kiyofumi

AU - Furuyama, Tohru

PY - 1988/12/1

Y1 - 1988/12/1

N2 - A CR-delay circuit technology for the realization of high-speed operation with a wide operational margin and minimized timing loss is discussed. It was applied to a 4-Mb CMOS DRAM, and the experimental results are described. A significant reduction in access time and cycle time was achieved.

AB - A CR-delay circuit technology for the realization of high-speed operation with a wide operational margin and minimized timing loss is discussed. It was applied to a 4-Mb CMOS DRAM, and the experimental results are described. A significant reduction in access time and cycle time was achieved.

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T2 - 1988 Symposium on VLSI Circuits - Digest of Technical Papers

Y2 - 22 August 1988 through 24 August 1988

ER -