New interconnect structure design methodology by Layout-design-based Interconnect Structure Optimization System (LADINOS)

S. Kobayashi, M. Edahiro, Y. Hayashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We present here the use of the performance predicting ECAD system, which is called Layout-design-based Interconnect Structure Optimization System (LADINOS), for the optimization of multilayer interconnect structures. This system is intended to be used to redesign current ULSI data on possible interconnect structures in the future and to measure the performance of such redesigned ULSIs. Despite the fact that system procedures include chip-size prediction, timing-driven assignment of interconnects to layers, and RC extraction which takes coupling capacitance into account, these procedures are performed very fast. We also give an example of the optimization of multi-layer interconnect structures for use in 0.13 μm-generation ULSIs with Al-interconnects.

Original languageEnglish
Title of host publicationProceedings of the IEEE 2000 International Interconnect Technology Conference, IITC 2000
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages12-14
Number of pages3
ISBN (Electronic)0780363272, 9780780363274
DOIs
Publication statusPublished - 2000
Externally publishedYes
Event3rd IEEE International Interconnect Technology Conference, IITC 2000 - Burlingame, United States
Duration: 2000 Jun 52000 Jun 7

Publication series

NameProceedings of the IEEE 2000 International Interconnect Technology Conference, IITC 2000

Conference

Conference3rd IEEE International Interconnect Technology Conference, IITC 2000
CountryUnited States
CityBurlingame
Period00/6/500/6/7

ASJC Scopus subject areas

  • Computer Science(all)

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