New LSI performance prediction model for interconnection analysis of future LSIs

Shuji Takahashi, Masato Edahiro, Yoshihiro Hayashi

Research output: Contribution to conferencePaper

6 Citations (Scopus)

Abstract

As the interconnection delays control the LSI performance, the LSI performance estimation at higher design level becomes more difficult. In this paper a new LSI performance model for the estimation is described, which is made up by adopting a new clock-skew model to the SUSPENS (Stanford University System Performance Simulator) model. Using the model, it is cleared that a specific block size, where the line delay overcomes the block cycle time, becomes shorter as the LSI generation proceeds.

Original languageEnglish
Pages51-56
Number of pages6
Publication statusPublished - 1998
Externally publishedYes
EventProceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98) - Yokohama, Jpn
Duration: 1998 Feb 101998 Feb 13

Other

OtherProceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98)
CityYokohama, Jpn
Period98/2/1098/2/13

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'New LSI performance prediction model for interconnection analysis of future LSIs'. Together they form a unique fingerprint.

  • Cite this

    Takahashi, S., Edahiro, M., & Hayashi, Y. (1998). New LSI performance prediction model for interconnection analysis of future LSIs. 51-56. Paper presented at Proceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98), Yokohama, Jpn, .