NEW METHOD FOR COMPACTION-BASED VLSI LAYOUT DESIGN.

Masaki Ishikawa, Tsuneo Matsuda, Takeshi Yoshimura, Satoshi Goto

Research output: Contribution to journalArticle

Abstract

The paper presents a new design method for custom LSI layouts. This method is based on layout compaction with automatic jog (wiring bend) generation in the layout. A dense chip design can be realized by this technique. Experimental results show that the chip size, designed by using the proposed layout method, is only 1. 2 to approx 1. 4 times larger than that resulting from manual layouts. Therefore, this compaction-based custom LSI layout design method is very effective in achieving a minimal chip layout design.

Original languageEnglish
Pages (from-to)46-58
Number of pages13
JournalNEC Research and Development
Issue number89
Publication statusPublished - 1988 Apr
Externally publishedYes

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Compaction
Electric wiring

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Ishikawa, M., Matsuda, T., Yoshimura, T., & Goto, S. (1988). NEW METHOD FOR COMPACTION-BASED VLSI LAYOUT DESIGN. NEC Research and Development, (89), 46-58.

NEW METHOD FOR COMPACTION-BASED VLSI LAYOUT DESIGN. / Ishikawa, Masaki; Matsuda, Tsuneo; Yoshimura, Takeshi; Goto, Satoshi.

In: NEC Research and Development, No. 89, 04.1988, p. 46-58.

Research output: Contribution to journalArticle

Ishikawa, M, Matsuda, T, Yoshimura, T & Goto, S 1988, 'NEW METHOD FOR COMPACTION-BASED VLSI LAYOUT DESIGN.', NEC Research and Development, no. 89, pp. 46-58.
Ishikawa M, Matsuda T, Yoshimura T, Goto S. NEW METHOD FOR COMPACTION-BASED VLSI LAYOUT DESIGN. NEC Research and Development. 1988 Apr;(89):46-58.
Ishikawa, Masaki ; Matsuda, Tsuneo ; Yoshimura, Takeshi ; Goto, Satoshi. / NEW METHOD FOR COMPACTION-BASED VLSI LAYOUT DESIGN. In: NEC Research and Development. 1988 ; No. 89. pp. 46-58.
@article{cfc74dc6bd814ec58ccc8fdf38a4120a,
title = "NEW METHOD FOR COMPACTION-BASED VLSI LAYOUT DESIGN.",
abstract = "The paper presents a new design method for custom LSI layouts. This method is based on layout compaction with automatic jog (wiring bend) generation in the layout. A dense chip design can be realized by this technique. Experimental results show that the chip size, designed by using the proposed layout method, is only 1. 2 to approx 1. 4 times larger than that resulting from manual layouts. Therefore, this compaction-based custom LSI layout design method is very effective in achieving a minimal chip layout design.",
author = "Masaki Ishikawa and Tsuneo Matsuda and Takeshi Yoshimura and Satoshi Goto",
year = "1988",
month = "4",
language = "English",
pages = "46--58",
journal = "NEC Research and Development",
issn = "0048-0436",
publisher = "NEC Media Products Ltd.",
number = "89",

}

TY - JOUR

T1 - NEW METHOD FOR COMPACTION-BASED VLSI LAYOUT DESIGN.

AU - Ishikawa, Masaki

AU - Matsuda, Tsuneo

AU - Yoshimura, Takeshi

AU - Goto, Satoshi

PY - 1988/4

Y1 - 1988/4

N2 - The paper presents a new design method for custom LSI layouts. This method is based on layout compaction with automatic jog (wiring bend) generation in the layout. A dense chip design can be realized by this technique. Experimental results show that the chip size, designed by using the proposed layout method, is only 1. 2 to approx 1. 4 times larger than that resulting from manual layouts. Therefore, this compaction-based custom LSI layout design method is very effective in achieving a minimal chip layout design.

AB - The paper presents a new design method for custom LSI layouts. This method is based on layout compaction with automatic jog (wiring bend) generation in the layout. A dense chip design can be realized by this technique. Experimental results show that the chip size, designed by using the proposed layout method, is only 1. 2 to approx 1. 4 times larger than that resulting from manual layouts. Therefore, this compaction-based custom LSI layout design method is very effective in achieving a minimal chip layout design.

UR - http://www.scopus.com/inward/record.url?scp=0023997126&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0023997126&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0023997126

SP - 46

EP - 58

JO - NEC Research and Development

JF - NEC Research and Development

SN - 0048-0436

IS - 89

ER -