Masaki Ishikawa, Tsuneo Matsuda, Takeshi Yoshimura, Satoshi Goto

Research output: Contribution to journalArticle


The paper presents a new design method for custom LSI layouts. This method is based on layout compaction with automatic jog (wiring bend) generation in the layout. A dense chip design can be realized by this technique. Experimental results show that the chip size, designed by using the proposed layout method, is only 1. 2 to approx 1. 4 times larger than that resulting from manual layouts. Therefore, this compaction-based custom LSI layout design method is very effective in achieving a minimal chip layout design.

Original languageEnglish
Pages (from-to)46-58
Number of pages13
JournalNEC Research and Development
Issue number89
Publication statusPublished - 1988 Apr
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Ishikawa, M., Matsuda, T., Yoshimura, T., & Goto, S. (1988). NEW METHOD FOR COMPACTION-BASED VLSI LAYOUT DESIGN. NEC Research and Development, (89), 46-58.