The paper presents a new design method for custom LSI layouts. This method is based on layout compaction with automatic jog (wiring bend) generation in the layout. A dense chip design can be realized by this technique. Experimental results show that the chip size, designed by using the proposed layout method, is only 1. 2 to approx 1. 4 times larger than that resulting from manual layouts. Therefore, this compaction-based custom LSI layout design method is very effective in achieving a minimal chip layout design.
|Number of pages||13|
|Journal||NEC Research and Development|
|Publication status||Published - 1988 Apr|
ASJC Scopus subject areas
- Electrical and Electronic Engineering