NEW MOS INTEGRATED CIRCUIT FABRICATION USING Si//3N//4 FILM SELF-ALIGNMENT LIFTOFF TECHNIQUES.

Toshiaki Yachi, Noriyoshi Yamauchi

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

A new MOS integrated circuits fabrication process that realizes self-aligned source and drain contact hole formation is described. This process utilizes a Si//3N//4 film self-alignment liftoff technique for selective oxidation (SALTS). Devices are fabricated using SALTS. It is shown that device packing density and speed show a 30-percent or more improvement over the conventional method at the same minimum lithographic feature size. It is also shown that Si//3N//4 film deposited using the sputtering method does not cause any degradation in device characteristics.

Original languageEnglish
Pages (from-to)243-247
Number of pages5
JournalIEEE Transactions on Electron Devices
VolumeED-29
Issue number2
Publication statusPublished - 1982 Feb
Externally publishedYes

Fingerprint

self alignment
integrated circuits
Integrated circuits
Fabrication
Oxidation
fabrication
Sputtering
oxidation
packing density
Degradation
electric contacts
sputtering
degradation
causes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Physics and Astronomy (miscellaneous)

Cite this

NEW MOS INTEGRATED CIRCUIT FABRICATION USING Si//3N//4 FILM SELF-ALIGNMENT LIFTOFF TECHNIQUES. / Yachi, Toshiaki; Yamauchi, Noriyoshi.

In: IEEE Transactions on Electron Devices, Vol. ED-29, No. 2, 02.1982, p. 243-247.

Research output: Contribution to journalArticle

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