New power-aware placement for region-based FPGA architecture combined with dynamic power gating by PCHM

Ce Li, Yiping Dong, Takahiro Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

The power consumption of FPGA is larger than that of ASIC to perform the same function in the same scaling. In this paper, we propose a Power Control Hard Macro (PCHM) based coarse-grained power gating FPGA architecture to dynamically reduce the power consumption. The algorithm of the placement based on sleep region is presented. After enhancing the CAD framework, a detailed study is given under different region size supported by the new FPGA architecture. As a result, the proposed architecture and the placement algorithm can reduce 51% power consumption on average compared with normal architecture.

Original languageEnglish
Title of host publicationProceedings of the International Symposium on Low Power Electronics and Design
Pages223-228
Number of pages6
DOIs
Publication statusPublished - 2011
Event17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011 - Fukuoka
Duration: 2011 Aug 12011 Aug 3

Other

Other17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
CityFukuoka
Period11/8/111/8/3

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Li, C., Dong, Y., & Watanabe, T. (2011). New power-aware placement for region-based FPGA architecture combined with dynamic power gating by PCHM. In Proceedings of the International Symposium on Low Power Electronics and Design (pp. 223-228). [5993640] https://doi.org/10.1109/ISLPED.2011.5993640