New power-aware placement for region-based FPGA architecture combined with dynamic power gating by PCHM

Ce Li*, Yiping Dong, Takahiro Watanabe

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

The power consumption of FPGA is larger than that of ASIC to perform the same function in the same scaling. In this paper, we propose a Power Control Hard Macro (PCHM) based coarse-grained power gating FPGA architecture to dynamically reduce the power consumption. The algorithm of the placement based on sleep region is presented. After enhancing the CAD framework, a detailed study is given under different region size supported by the new FPGA architecture. As a result, the proposed architecture and the placement algorithm can reduce 51% power consumption on average compared with normal architecture.

Original languageEnglish
Title of host publicationIEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
Pages223-228
Number of pages6
DOIs
Publication statusPublished - 2011 Sep 19
Event17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011 - Fukuoka, Japan
Duration: 2011 Aug 12011 Aug 3

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Other

Other17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
Country/TerritoryJapan
CityFukuoka
Period11/8/111/8/3

ASJC Scopus subject areas

  • Engineering(all)

Fingerprint

Dive into the research topics of 'New power-aware placement for region-based FPGA architecture combined with dynamic power gating by PCHM'. Together they form a unique fingerprint.

Cite this