New power-efficient FPGA design combining with region-constrained placement and multiple power domains

Ce Li, Yiping Dong, Takahiro Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Multiple power domain design architectures have been studied for the power-efficient FPGAs. But, most of these researches pay attention on the clustered logic block's finegrain power gating which increases the FPGA size significantly. This paper presents a fast placement algorithm for coarsegrain FPGAs architecture, by which the circuit with multiple power domains is mapped into several regions for low power consumption. Each region uses one or several sleep transistors in order to conserve leakage energy. Using the CAD framework, we discuss the power efficiency of sleep region FPGA architecture by using the benchmarks assumed in multiple power domains. Simulation result shows that 9.1% power consumption of FPGA can be reduced on average by the proposed placement algorithm, compared to the traditional algorithm. Furthermore, when the dual power domains are individually power-on and -off, our proposed method can reduce the power more than 20%.

Original languageEnglish
Title of host publication2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011
Pages69-72
Number of pages4
DOIs
Publication statusPublished - 2011
Event2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011 - Bordeaux
Duration: 2011 Jun 262011 Jun 29

Other

Other2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011
CityBordeaux
Period11/6/2611/6/29

Fingerprint

Field programmable gate arrays (FPGA)
Electric power utilization
Computer aided design
Transistors
Networks (circuits)
Sleep

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Li, C., Dong, Y., & Watanabe, T. (2011). New power-efficient FPGA design combining with region-constrained placement and multiple power domains. In 2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011 (pp. 69-72). [5981221] https://doi.org/10.1109/NEWCAS.2011.5981221

New power-efficient FPGA design combining with region-constrained placement and multiple power domains. / Li, Ce; Dong, Yiping; Watanabe, Takahiro.

2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011. 2011. p. 69-72 5981221.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Li, C, Dong, Y & Watanabe, T 2011, New power-efficient FPGA design combining with region-constrained placement and multiple power domains. in 2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011., 5981221, pp. 69-72, 2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011, Bordeaux, 11/6/26. https://doi.org/10.1109/NEWCAS.2011.5981221
Li C, Dong Y, Watanabe T. New power-efficient FPGA design combining with region-constrained placement and multiple power domains. In 2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011. 2011. p. 69-72. 5981221 https://doi.org/10.1109/NEWCAS.2011.5981221
Li, Ce ; Dong, Yiping ; Watanabe, Takahiro. / New power-efficient FPGA design combining with region-constrained placement and multiple power domains. 2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011. 2011. pp. 69-72
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